| Current Path : /compat/linux/proc/68247/root/compat/linux/proc/68247/root/compat/linux/proc/68247/root/usr/lib32/ |
FreeBSD hs32.drive.ne.jp 9.1-RELEASE FreeBSD 9.1-RELEASE #1: Wed Jan 14 12:18:08 JST 2015 root@hs32.drive.ne.jp:/sys/amd64/compile/hs32 amd64 |
| Current File : //compat/linux/proc/68247/root/compat/linux/proc/68247/root/compat/linux/proc/68247/root/usr/lib32/libpmc.so.5 |
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BUS_TRANS_DEF BUS_TRANS_IFETCH BUS_TRANS_INVAL BUS_TRANS_IO BUS_TRANS_MEM BUS_TRANS_P BUS_TRANS_PWR BUS_TRANS_RFO BUS_TRANS_WB CMP_SNOOP CPU_CLK_UNHALTED.BUS CPU_CLK_UNHALTED.CORE_P CPU_CLK_UNHALTED.NO_OTHER CYCLES_L1I_MEM_STALLED DATA_TLB_MISSES.DTLB_MISS DATA_TLB_MISSES.DTLB_MISS_LD DATA_TLB_MISSES.DTLB_MISS_ST DATA_TLB_MISSES.UTLB_MISS_LD DELAYED_BYPASS.FP DELAYED_BYPASS.LOAD DELAYED_BYPASS.SIMD DIV.AR DIV.S DTLB_MISSES.ANY DTLB_MISSES.L0_MISS_LD DTLB_MISSES.MISS_LD DTLB_MISSES.MISS_ST EIST_TRANS ESP.ADDITIONS ESP.SYNCH EXT_SNOOP FP_ASSIST FP_ASSIST.AR FP_COMP_OPS_EXE FP_MMX_TRANS_TO_FP FP_MMX_TRANS_TO_MMX HW_INT_RCV ICACHE.ACCESSES ICACHE.MISSES IDLE_DURING_DIV ILD_STALL INST_QUEUE.FULL INST_RETIRED.OTHER ITLB.FLUSH ITLB.LARGE_MISS ITLB.MISSES ITLB.SMALL_MISS ITLB_MISS_RETIRED L1D_ALL_CACHE_REF L1D_ALL_REF L1D_CACHE.LD L1D_CACHE.ST L1D_CACHE_LOCK L1D_CACHE_LOCK_DURATION L1D_M_EVICT L1D_M_REPL L1D_PEND_MISS L1D_PREFETCH.REQUESTS L1D_REPL L1D_SPLIT.LOADS L1D_SPLIT.STORES L1I_MISSES L1I_READS L2_ADS L2_DBUS_BUSY_RD L2_IFETCH L2_LD L2_LINES_IN L2_LINES_OUT L2_LOCK L2_M_LINES_IN L2_M_LINES_OUT L2_NO_REQ L2_REJECT_BUSQ L2_RQSTS L2_RQSTS.SELF.DEMAND.I_STATE L2_RQSTS.SELF.DEMAND.MESI L2_ST LOAD_BLOCK.L1D LOAD_BLOCK.OVERLAP_STORE LOAD_BLOCK.STA LOAD_BLOCK.STD LOAD_BLOCK.UNTIL_RETIRE LOAD_HIT_PRE MACHINE_CLEARS.SMC MACHINE_NUKES.MEM_ORDER MACRO_INSTS.ALL_DECODED MACRO_INSTS.CISC_DECODED MEMORY_DISAMBIGUATION.RESET MEMORY_DISAMBIGUATION.SUCCESS MEM_LOAD_RETIRED.DTLB_MISS MEM_LOAD_RETIRED.L2_HIT MEM_LOAD_RETIRED.L2_LINE_MISS MEM_LOAD_RETIRED.L2_MISS PAGE_WALKS.CYCLES PAGE_WALKS.WALKS PREFETCH.PREFETCHNTA PREFETCH.PREFETCHT0 PREFETCH.SW_L2 RAT_STALLS.ANY RAT_STALLS.FLAGS RAT_STALLS.FPSW RAT_STALLS.PARTIAL_CYCLES RAT_STALLS.ROB_READ_PORT RESOURCE_STALLS.ANY RESOURCE_STALLS.BR_MISS_CLEAR RESOURCE_STALLS.FPCW RESOURCE_STALLS.LD_ST RESOURCE_STALLS.ROB_FULL RESOURCE_STALLS.RS_FULL RS_UOPS_DISPATCHED RS_UOPS_DISPATCHED.PORT0 RS_UOPS_DISPATCHED.PORT1 RS_UOPS_DISPATCHED.PORT2 RS_UOPS_DISPATCHED.PORT3 RS_UOPS_DISPATCHED.PORT4 RS_UOPS_DISPATCHED.PORT5 SB_DRAIN_CYCLES SEGMENT_REG_LOADS.ANY SEG_REG_RENAMES.ANY SEG_REG_RENAMES.DS SEG_REG_RENAMES.ES SEG_REG_RENAMES.FS SEG_REG_RENAMES.GS SEG_RENAME_STALLS.ANY SEG_RENAME_STALLS.DS SEG_RENAME_STALLS.ES SEG_RENAME_STALLS.FS SEG_RENAME_STALLS.GS SIMD_ASSIST SIMD_INST_RETIRED.ANY SIMD_INST_RETIRED.VECTOR SIMD_SAT_INSTR_RETIRED SIMD_SAT_UOP_EXEC.AR SIMD_SAT_UOP_EXEC.S SIMD_UOPS_EXEC.AR SIMD_UOPS_EXEC.S SIMD_UOP_TYPE_EXEC.LOGICAL.AR SIMD_UOP_TYPE_EXEC.LOGICAL.S SIMD_UOP_TYPE_EXEC.MUL.AR SIMD_UOP_TYPE_EXEC.MUL.S SIMD_UOP_TYPE_EXEC.PACK.AR SIMD_UOP_TYPE_EXEC.PACK.S SIMD_UOP_TYPE_EXEC.SHIFT.AR SIMD_UOP_TYPE_EXEC.SHIFT.S SIMD_UOP_TYPE_EXEC.UNPACK.AR SIMD_UOP_TYPE_EXEC.UNPACK.S SNOOP_STALL_DRV SSE_PRE_EXEC.L2 SSE_PRE_EXEC.STORES SSE_PRE_MISS.L1 SSE_PRE_MISS.L2 SSE_PRE_MISS.NTA STORE_BLOCK.ORDER STORE_BLOCK.SNOOP STORE_FORWARDS.GOOD UOPS_RETIRED.ANY UOPS_RETIRED.FUSED UOPS_RETIRED.LD_IND_BR UOPS_RETIRED.MACRO_FUSION UOPS_RETIRED.NON_FUSED UOPS_RETIRED.STD_STA X87_COMP_OPS_EXE.ANY.AR X87_COMP_OPS_EXE.ANY.S X87_OPS_RETIRED.ANY X87_OPS_RETIRED.FXCH BAClears BTB_Misses Br_BAC_Missp_Exec Br_Bogus Br_Call_Exec Br_Call_Missp_Exec Br_Cnd_Exec Br_Cnd_Missp_Exec Br_Ind_Call_Exec Br_Ind_Exec Br_Ind_Missp_Exec Br_Inst_Exec Br_Instr_Decoded Br_Instr_Ret Br_MisPred_Ret Br_MisPred_Taken_Ret Br_Missp_Exec Br_Ret_BAC_Missp_Exec Br_Ret_Exec Br_Ret_Missp_Exec Br_Taken_Ret Bus_BNR_Clocks Bus_DRDY_Clocks Bus_Data_Rcv Bus_Locks_Clocks Bus_Not_In_Use Bus_Req_Outstanding Bus_Snoop_Stall Bus_Snoops Bus_Trans_Any Bus_Trans_Brd Bus_Trans_Burst Bus_Trans_Def Bus_Trans_IO Bus_Trans_Ifetch Bus_Trans_Inval Bus_Trans_Mem Bus_Trans_P Bus_Trans_Pwr Bus_Trans_RFO Bus_Trans_WB Cycles_Div_Busy Cycles_Int_Masked Cycles_Int_Pending_Masked DCU_Snoop_To_Share DCache_Cache_LD DCache_Cache_Lock DCache_Cache_ST DCache_M_Evict DCache_M_Repl DCache_Pend_Miss DCache_Repl Data_Mem_Cache_Ref Data_Mem_Ref Dbus_Busy Dbus_Busy_Rd Div Dtlb_Miss ESP_Uops EST_Trans FP_Assist FP_Comp_Instr_Ret FP_Comps_Op_Exe FP_MMX_Trans Fused_Ld_Uops_Ret Fused_St_Uops_Ret Fused_Uops_Ret HW_Int_Rx ICache_Misses ICache_Reads IFU_Mem_Stall ILD_Stall ITLB_Misses L1_Pref_Req L2_IFetch L2_Lines_In L2_Lines_Out L2_M_Lines_In L2_M_Lines_Out L2_No_Request_Cycles L2_Reject_Cycles L2_Rqsts LD_Blocks LLC_Misses LLC_Reference MMX_Assist MMX_FP_Trans MMX_Instr_Exec MMX_Instr_Ret Misalign_Mem_Ref Mul NonHlt_Ref_Cycles Pref_Rqsts_Dn Pref_Rqsts_Up Resource_Stall SD_Drains SIMD_FP_DP_P_Comp_Ret SIMD_FP_DP_P_Ret SIMD_FP_DP_S_Comp_Ret SIMD_FP_DP_S_Ret SIMD_FP_SP_P_Comp_Ret SIMD_FP_SP_Ret SIMD_FP_SP_S_Comp_Ret SIMD_FP_SP_S_Ret SIMD_Int_128_Ret SIMD_Int_Pari_Exec SIMD_Int_Pck_Exec SIMD_Int_Plog_Exec SIMD_Int_Pmul_Exec SIMD_Int_Psft_Exec SIMD_Int_Sat_Exec SIMD_Int_Upck_Exec SMC_Detected SSE_NTStores_Miss SSE_NTStores_Ret SSE_PrefNta_Miss SSE_PrefNta_Ret SSE_PrefT1_Miss SSE_PrefT1_Ret SSE_PrefT2_Miss SSE_PrefT2_Ret Seg_Reg_Loads Serial_Execution_Cycles Thermal_Trip Unfusion Unhalted_Core_Cycles CYCLES_INT_MASKED CYCLES_INT_PENDING_AND_MASKED INST_RETIRED.VM_H L1D_CACHE_LD L1D_CACHE_ST MACHINE_NUKES.SMC MACRO_INSTS.DECODED MEM_LOAD_RETIRED.L1D_MISS PAGE_WALKS.COUNT SEGMENT_REG_LOADS SIMD_SAT_UOP_EXEC SIMD_UOPS_EXEC SIMD_UOP_TYPE_EXEC.ARITHMETIC SIMD_UOP_TYPE_EXEC.LOGICAL SIMD_UOP_TYPE_EXEC.MUL SIMD_UOP_TYPE_EXEC.PACK SIMD_UOP_TYPE_EXEC.SHIFT SIMD_UOP_TYPE_EXEC.UNPACK SSE_PRE_EXEC.L1 SSE_PRE_EXEC.NTA SB_DRAIN.ANY STORE_BLOCKS.AT_RET STORE_BLOCKS.L1D_BLOCK PARTIAL_ADDRESS_ALIAS DTLB_LOAD_MISSES.ANY DTLB_LOAD_MISSES.STLB_HIT DTLB_LOAD_MISSES.PDE_MISS MEM_INST_RETIRED.LOADS MEM_INST_RETIRED.STORES MEM_STORE_RETIRED.DTLB_MISS UOPS_ISSUED.ANY UOPS_ISSUED.STALLED_CYCLES UOPS_ISSUED.FUSED MEM_UNCORE_RETIRED.LOCAL_DRAM FP_COMP_OPS_EXE.X87 FP_COMP_OPS_EXE.MMX FP_COMP_OPS_EXE.SSE_FP FP_COMP_OPS_EXE.SSE2_INTEGER FP_COMP_OPS_EXE.SSE_FP_PACKED FP_COMP_OPS_EXE.SSE_FP_SCALAR SIMD_INT_128.PACKED_MPY SIMD_INT_128.PACKED_SHIFT SIMD_INT_128.PACK SIMD_INT_128.UNPACK SIMD_INT_128.PACKED_LOGICAL SIMD_INT_128.PACKED_ARITH SIMD_INT_128.SHUFFLE_MOVE LOAD_DISPATCH.RS LOAD_DISPATCH.RS_DELAYED LOAD_DISPATCH.MOB LOAD_DISPATCH.ANY ARITH.CYCLES_DIV_BUSY ARITH.MUL INST_QUEUE_WRITES INST_DECODED.DEC0 TWO_UOP_INSTS_DECODED INST_QUEUE_WRITE_CYCLES LSD_OVERFLOW L2_RQSTS.LD_HIT L2_RQSTS.LD_MISS L2_RQSTS.LOADS L2_RQSTS.RFO_HIT L2_RQSTS.RFO_MISS L2_RQSTS.RFOS L2_RQSTS.IFETCH_HIT L2_RQSTS.IFETCH_MISS L2_RQSTS.IFETCHES L2_RQSTS.PREFETCH_HIT L2_RQSTS.PREFETCH_MISS L2_RQSTS.PREFETCHES L2_RQSTS.MISS L2_RQSTS.REFERENCES L2_DATA_RQSTS.DEMAND.I_STATE L2_DATA_RQSTS.DEMAND.S_STATE L2_DATA_RQSTS.DEMAND.E_STATE L2_DATA_RQSTS.DEMAND.M_STATE L2_DATA_RQSTS.DEMAND.MESI L2_DATA_RQSTS.PREFETCH.MESI L2_DATA_RQSTS.ANY L2_WRITE.RFO.I_STATE L2_WRITE.RFO.S_STATE L2_WRITE.RFO.M_STATE L2_WRITE.RFO.HIT L2_WRITE.RFO.MESI L2_WRITE.LOCK.I_STATE L2_WRITE.LOCK.S_STATE L2_WRITE.LOCK.E_STATE L2_WRITE.LOCK.M_STATE L2_WRITE.LOCK.HIT L2_WRITE.LOCK.MESI L1D_WB_L2.I_STATE L1D_WB_L2.S_STATE L1D_WB_L2.E_STATE L1D_WB_L2.M_STATE L1D_WB_L2.MESI L3_LAT_CACHE.REFERENCE L3_LAT_CACHE.MISS CPU_CLK_UNHALTED.THREAD_P CPU_CLK_UNHALTED.REF_P L1D_CACHE_LD.I_STATE L1D_CACHE_LD.S_STATE L1D_CACHE_LD.E_STATE L1D_CACHE_LD.M_STATE L1D_CACHE_LD.MESI L1D_CACHE_ST.S_STATE L1D_CACHE_ST.E_STATE L1D_CACHE_ST.M_STATE L1D_CACHE_LOCK.HIT L1D_CACHE_LOCK.S_STATE L1D_CACHE_LOCK.E_STATE L1D_CACHE_LOCK.M_STATE L1D_ALL_REF.ANY L1D_ALL_REF.CACHEABLE DTLB_MISSES.WALK_COMPLETED DTLB_MISSES.STLB_HIT DTLB_MISSES.PDE_MISS L1D_PREFETCH.MISS L1D_PREFETCH.TRIGGERS L1D.REPL L1D.M_REPL L1D.M_EVICT L1D.M_SNOOP_EVICT L1D_CACHE_LOCK_FB_HIT CACHE_LOCK_CYCLES.L1D_L2 CACHE_LOCK_CYCLES.L1D IO_TRANSACTIONS L1I.HITS L1I.MISSES L1I.READS L1I.CYCLES_STALLED LARGE_ITLB.HIT ITLB_MISSES.ANY ITLB_MISSES.WALK_COMPLETED ILD_STALL.LCP ILD_STALL.MRU ILD_STALL.IQ_FULL ILD_STALL.REGEN ILD_STALL.ANY BR_INST_EXEC.COND BR_INST_EXEC.DIRECT BR_INST_EXEC.NON_CALLS BR_INST_EXEC.RETURN_NEAR BR_INST_EXEC.DIRECT_NEAR_CALL BR_INST_EXEC.NEAR_CALLS BR_INST_EXEC.TAKEN BR_INST_EXEC.ANY BR_MISP_EXEC.COND BR_MISP_EXEC.DIRECT BR_MISP_EXEC.NON_CALLS BR_MISP_EXEC.RETURN_NEAR BR_MISP_EXEC.DIRECT_NEAR_CALL BR_MISP_EXEC.NEAR_CALLS BR_MISP_EXEC.TAKEN BR_MISP_EXEC.ANY RESOURCE_STALLS.LOAD RESOURCE_STALLS.STORE RESOURCE_STALLS.MXCSR RESOURCE_STALLS.OTHER MACRO_INSTS.FUSIONS_DECODED BACLEAR_FORCE_IQ LSD.UOPS UOPS_EXECUTED.PORT0 UOPS_EXECUTED.PORT1 UOPS_EXECUTED.PORT2_CORE UOPS_EXECUTED.PORT3_CORE UOPS_EXECUTED.PORT4_CORE UOPS_EXECUTED.PORT5 UOPS_EXECUTED.PORT015 UOPS_EXECUTED.PORT234 OFFCORE_REQUESTS_SQ_FULL OFF_CORE_RESPONSE_0 SNOOP_RESPONSE.HIT SNOOP_RESPONSE.HITE SNOOP_RESPONSE.HITM OFF_CORE_RESPONSE_1 INST_RETIRED.X87 INST_RETIRED.MMX UOPS_RETIRED.RETIRE_SLOTS UOPS_RETIRED.MACRO_FUSED MACHINE_CLEARS.CYCLES MACHINE_CLEARS.MEM_ORDER BR_INST_RETIRED.ALL_BRANCHES BR_INST_RETIRED.CONDITIONAL BR_INST_RETIRED.NEAR_CALL BR_MISP_RETIRED.ALL_BRANCHES BR_MISP_RETIRED.NEAR_CALL MEM_LOAD_RETIRED.L1D_HIT MEM_LOAD_RETIRED.L3_MISS MEM_LOAD_RETIRED.HIT_LFB FP_MMX_TRANS.TO_FP FP_MMX_TRANS.TO_MMX FP_MMX_TRANS.ANY UOPS_DECODED.MS UOPS_DECODED.ESP_FOLDING UOPS_DECODED.ESP_SYNC RAT_STALLS.REGISTERS RAT_STALLS.SCOREBOARD SEG_RENAME_STALLS ES_REG_RENAMES UOP_UNFUSION BPU_MISSED_CALL_RET BACLEAR.CLEAR BACLEAR.BAD_TARGET BPU_CLEARS.EARLY BPU_CLEARS.LATE L2_TRANSACTIONS.LOAD L2_TRANSACTIONS.RFO L2_TRANSACTIONS.IFETCH L2_TRANSACTIONS.PREFETCH L2_TRANSACTIONS.L1D_WB L2_TRANSACTIONS.FILL L2_TRANSACTIONS.WB L2_TRANSACTIONS.ANY L2_LINES_IN.S_STATE L2_LINES_IN.E_STATE L2_LINES_IN.ANY L2_LINES_OUT.DEMAND_CLEAN L2_LINES_OUT.DEMAND_DIRTY L2_LINES_OUT.PREFETCH_CLEAN L2_LINES_OUT.PREFETCH_DIRTY L2_LINES_OUT.ANY SQ_MISC.SPLIT_LOCK SQ_FULL_STALL_CYCLES FP_ASSIST.ALL FP_ASSIST.OUTPUT FP_ASSIST.INPUT SIMD_INT_64.PACKED_MPY SIMD_INT_64.PACKED_SHIFT SIMD_INT_64.PACK SIMD_INT_64.UNPACK SIMD_INT_64.PACKED_LOGICAL SIMD_INT_64.PACKED_ARITH SIMD_INT_64.SHUFFLE_MOVE SB_FORWARD.ANY LOAD_BLOCK.ADDRESS_OFFSET SB_DRAIN.CYCLES MISALIGN_MEM_REF.LOAD MISALIGN_MEM_REF.STORE MISALIGN_MEM_REF.ANY STORE_BLOCKS.NOT_STA STORE_BLOCKS.STA STORE_BLOCKS.ANY DTLB_LOAD_MISSES.PDP_MISS MEMORY_DISAMBIGURATION.RESET HW_INT.RCV HW_INT.CYCLES_MASKED L2_WRITE.RFO.E_STATE UOPS_DECODED.DEC0 L1D_CACHE_ST.I_STATE L1D_CACHE_ST.MESI DTLB_MISSES.PDP_MISS SSE_MEM_EXEC.NTA SSE_MEM_EXEC.STREAMING_STORES SFENCE_CYCLES EPT.EPDE_MISS EPT.EPDPE_HIT EPT.EPDPE_MISS IFU_IVC.FULL IFU_IVC.L1I_EVICTION L1I_OPPORTUNISTIC_HITS ITLB_MISSES.WALK_CYCLES ITLB_MISSES.PMH_BUSY_CYCLES ITLB_MISSES.STLB_HIT ITLB_MISSES.PDE_MISS ITLB_MISSES.PDP_MISS OFFCORE_REQUESTS.DEMAND.RFO OFFCORE_REQUESTS.ANY.READ OFFCORE_REQUESTS.ANY.RFO OFFCORE_REQUESTS.UNCACHED_MEM OFFCORE_REQUESTS.ANY PIC_ACCESSES.TPR_READS PIC_ACCESSES.TPR_WRITES MACHINE_CLEARS.FUSION_ASSIST BPU_CLEARS.ANY L2_HW_PREFETCH.HIT L2_HW_PREFETCH.ALLOC L2_HW_PREFETCH.DATA_TRIGGER L2_HW_PREFETCH.CODE_TRIGGER L2_HW_PREFETCH.DCA_TRIGGER L2_HW_PREFETCH.KICK_START SQ_MISC.PROMOTION SQ_MISC.PROMOTION_POST_GO SQ_MISC.LRU_HINTS SQ_MISC.FILL_DROPPED LD_BLOCKS.DATA_UNKNOWN LD_BLOCKS.STORE_FORWARD LD_BLOCKS.NO_SR LD_BLOCKS.ALL_BLOCK MISALIGN_MEM_REF.LOADS MISALIGN_MEM_REF.STORES INT_MISC.RECOVERY_CYCLES INT_MISC.RAT_STALL_CYCLES SIMD_FP_256.PACKED_SINGLE SIMD_FP_256.PACKED_DOUBLE ARITH.FPU_DIV_ACTIVE INSTS_WRITTEN_TO_IQ.INSTS L2_RQSTS.DEMAND_DATA_RD_HIT L2_RQSTS.ALL_DEMAND_DATA_RD L2_RQSTS.RFO_HITS L2_RQSTS.ALL_RFO L2_RQSTS.CODE_RD_HIT L2_RQSTS.CODE_RD_MISS L2_RQSTS.ALL_CODE_RD L2_RQSTS.PF_HIT L2_RQSTS.PF_MISS L2_RQSTS.ALL_PF L2_STORE_LOCK_RQSTS.MISS L2_STORE_LOCK_RQSTS.HIT_E L2_STORE_LOCK_RQSTS.HIT_M L2_STORE_LOCK_RQSTS.ALL L2_L1D_WB_RQSTS.HIT_E L2_L1D_WB_RQSTS.HIT_M LONGEST_LAT_CACHE.REFERENCE LONGEST_LAT_CACHE.MISS L1D_PEND_MISS.PENDING DTLB_STORE_MISSES.STLB_HIT LOAD_HIT_PRE.SW_PF LOAD_HIT_PER.HW_PF HW_PRE_REQ.DL1_MISS L1D.REPLACEMENT L1D.ALLOCATED_IN_M L1D.EVICTION L1D.ALL_M_REPLACEMENT RESOURCE_STALLS2.ALL_FL_EMPTY RESOURCE_STALLS2.BOB_FULL RESOURCE_STALLS2.OOO_RSRC CPL_CYCLES.RING0 CPL_CYCLES.RING123 RS_EVENTS.EMPTY_CYCLES IDQ.EMPTY IQD.MITE_UOPS IDQ.DSB_UOPS IDQ.MS_DSB_UOPS IDQ.MS_MITE_UOPS IDQ.MS_UOPS ITLB_MISSES.WALK_DURATION BR_INST_EXEC.DIRECT_JMP BR_INST_EXEC.NONTAKEN BR_INST_EXE.ALL_BRANCHES BR_MISP_EXEC.NONTAKEN BR_MISP_EXEC.ALL_BRANCHES IDQ_UOPS_NOT_DELIVERED.CORE UOPS_DISPATCHED_PORT.PORT_0 UOPS_DISPATCHED_PORT.PORT_1 UOPS_DISPATCHED_PORT.PORT_2 UOPS_DISPATCHED_PORT.PORT_3 UOPS_DISPATCHED_PORT.PORT_4 UOPS_DISPATCHED_PORT.PORT_5 RESOURCE_STALLS.LB RESOURCE_STALLS.SB RESOURCE_STALLS.ROB RESOURCE_STALLS.FCSW DSB2MITE_SWITCHES.COUNT DSB_FILL.OTHER_CANCEL DSB_FILL.EXCEED_DSB_LINES DSB_FILL.ALL_CANCEL ITLB.ITLB_FLUSH OFFCORE_REQUESTS.DEMAND_RFO OFFCORE_REQUESTS.ALL_DATA_RD UOPS_DISPATCHED.THREAD UOPS_DISPATCHED.CORE AGU_BYPASS_CANCEL.COUNT TLB_FLUSH.DTLB_THREAD TLB_FLUSH.STLB_ANY INST_RETIRED.PREC_DIST OTHER_ASSISTS.AVX_STORE OTHER_ASSISTS.AVX_TO_SSE OTHER_ASSISTS.SSE_TO_AVX UOPS_RETIRED.ALL MACHINE_CLEARS.MASKMOV BR_INST_RETIRED.ALL_BRANCH BR_INST_RETIRED.NEAR_RETURN BR_INST_RETIRED.NOT_TAKEN BR_INST_RETIRED.NEAR_TAKEN BR_INST_RETIRED.FAR_BRANCH BR_MISP_RETIRED.CONDITIONAL BR_MISP_RETIRED.NOT_TAKEN BR_MISP_RETIRED.TAKEN FP_ASSIST.X87_OUTPUT FP_ASSIST.X87_INPUT FP_ASSIST.SIMD_OUTPUT FP_ASSIST.SIMD_INPUT FP_ASSIST.ANY ROB_MISC_EVENTS.LBR_INSERTS MEM_UOP_RETIRED.LOADS MEM_UOP_RETIRED.STORES MEM_UOP_RETIRED.STLB_MISS MEM_UOP_RETIRED.LOCK MEM_UOP_RETIRED.SPLIT MEM_UOP_RETIRED_ALL MEM_LOAD_UOPS_RETIRED.L1_HIT MEM_LOAD_UOPS_RETIRED.L2_HIT MEM_LOAD_UOPS_RETIRED.LLC_HIT MEM_LOAD_UOPS_RETIRED.HIT_LFB L2_TRANS.DEMAND_DATA_RD L2_TRANS.RF0 L2_TRANS.CODE_RD L2_TRANS.ALL_PF L2_TRANS.L1D_WB L2_TRANS.L2_FILL L2_TRANS.L2_WB L2_TRANS.ALL_REQUESTS L2_LINES_IN.I L2_LINES_IN.S L2_LINES_IN.E L2_LINES-IN.ALL L2_LINES_OUT.PF_CLEAN L2_LINES_OUT.PF_DIRTY L2_LINES_OUT.DIRTY_ALL MISALIGN_MEMORY.STORE DTLB_LOAD_MISSES.WALK_CYCLES MEM_UNCORE_RETIRED.LOCAL_HITM DTLB_MISSES.WALK_CYCLES EPT.WALK_CYCLES SNOOPQ_REQUESTS.CODE SNOOPQ_REQUESTS.DATA SNOOPQ_REQUESTS.INVALIDATE BR_INST_RETIRED.ANY_P BR_MISP_RETIRED.ANY_P UOPS_DECODED.STALL_CYCLES THREAD_ACTIVE UCLOCK GQ_CYCLES_FULL.READ_TRACKER GQ_CYCLES_FULL.WRITE_TRACKER GQ_ALLOC.READ_TRACKER GQ_ALLOC.RT_L3_MISS GQ_ALLOC.RT_TO_L3_RESP GQ_ALLOC.RT_TO_RTID_ACQUIRED GQ_ALLOC.WT_TO_RTID_ACQUIRED GQ_ALLOC.WRITE_TRACKER GQ_ALLOC.PEER_PROBE_TRACKER GQ_DATA.FROM_QPI GQ_DATA.FROM_QMC GQ_DATA.FROM_L3 GQ_DATA.FROM_CORES_02 GQ_DATA.FROM_CORES_13 GQ_DATA.TO_QPI_QMC GQ_DATA.TO_L3 GQ_DATA.TO_CORES SNP_RESP_TO_LOCAL_HOME.WB SNP_RESP_TO_REMOTE_HOME.WB SNP_RESP_TO_REMOTE_HOME.HITM L3_HITS.READ L3_HITS.WRITE L3_HITS.PROBE L3_HITS.ANY L3_MISS.READ L3_MISS.WRITE L3_MISS.PROBE L3_MISS.ANY L3_LINES_IN.M_STATE L3_LINES_IN.E_STATE L3_LINES_IN.S_STATE L3_LINES_IN.F_STATE L3_LINES_IN.ANY L3_LINES_OUT.M_STATE L3_LINES_OUT.E_STATE L3_LINES_OUT.S_STATE L3_LINES_OUT.I_STATE L3_LINES_OUT.F_STATE L3_LINES_OUT.ANY QHL_REQUESTS.IOH_READS QHL_REQUESTS.IOH_WRITES QHL_REQUESTS.REMOTE_READS QHL_REQUESTS.REMOTE_WRITES QHL_REQUESTS.LOCAL_READS QHL_REQUESTS.LOCAL_WRITES QHL_CYCLES_FULL.IOH QHL_CYCLES_FULL.REMOTE QHL_CYCLES_FULL.LOCAL QHL_CYCLES_NOT_EMPTY.IOH QHL_CYCLES_NOT_EMPTY.REMOTE QHL_CYCLES_NOT_EMPTY.LOCAL QHL_OCCUPANCY.IOH QHL_OCCUPANCY.REMOTE QHL_OCCUPANCY.LOCAL QHL_ADDRESS_CONFLICTS.2WAY QHL_ADDRESS_CONFLICTS.3WAY QHL_CONFLICT_CYCLES.IOH QHL_CONFLICT_CYCLES.REMOTE QHL_CONFLICT_CYCLES.LOCAL QHL_TO_QMC_BYPASS QMC_NORMAL_FULL.READ.CH0 QMC_NORMAL_FULL.READ.CH1 QMC_NORMAL_FULL.READ.CH2 QMC_NORMAL_FULL.WRITE.CH0 QMC_NORMAL_FULL.WRITE.CH1 QMC_NORMAL_FULL.WRITE.CH2 QMC_ISOC_FULL.READ.CH0 QMC_ISOC_FULL.READ.CH1 QMC_ISOC_FULL.READ.CH2 QMC_ISOC_FULL.WRITE.CH0 QMC_ISOC_FULL.WRITE.CH1 QMC_ISOC_FULL.WRITE.CH2 QMC_BUSY.READ.CH0 QMC_BUSY.READ.CH1 QMC_BUSY.READ.CH2 QMC_BUSY.WRITE.CH0 QMC_BUSY.WRITE.CH1 QMC_BUSY.WRITE.CH2 QMC_OCCUPANCY.CH0 QMC_OCCUPANCY.CH1 QMC_OCCUPANCY.CH2 QMC_ISSOC_OCCUPANCY.CH0 QMC_ISSOC_OCCUPANCY.CH1 QMC_ISSOC_OCCUPANCY.CH2 QMC_ISSOC_READS.ANY QMC_NORMAL_READS.CH0 QMC_NORMAL_READS.CH1 QMC_NORMAL_READS.CH2 QMC_NORMAL_READS.ANY QMC_HIGH_PRIORITY_READS.CH0 QMC_HIGH_PRIORITY_READS.CH1 QMC_HIGH_PRIORITY_READS.CH2 QMC_HIGH_PRIORITY_READS.ANY QMC_WRITES.FULL.CH0 QMC_WRITES.FULL.CH1 QMC_WRITES.FULL.CH2 QMC_WRITES.FULL.ANY QMC_WRITES.PARTIAL.CH0 QMC_WRITES.PARTIAL.CH1 QMC_WRITES.PARTIAL.CH2 QMC_WRITES.PARTIAL.ANY QMC_CANCEL.CH0 QMC_CANCEL.CH1 QMC_CANCEL.CH2 QMC_CANCEL.ANY QMC_PRIORITY_UPDATES.CH0 QMC_PRIORITY_UPDATES.CH1 QMC_PRIORITY_UPDATES.CH2 QMC_PRIORITY_UPDATES.ANY QHL_FRC_ACK_CNFLTS.LOCAL QPI_TX_HEADER.BUSY.LINK_0 QPI_TX_HEADER.BUSY.LINK_1 DRAM_OPEN.CH0 DRAM_OPEN.CH1 DRAM_OPEN.CH2 DRAM_PAGE_CLOSE.CH0 DRAM_PAGE_CLOSE.CH1 DRAM_PAGE_CLOSE.CH2 DRAM_PAGE_MISS.CH0 DRAM_PAGE_MISS.CH1 DRAM_PAGE_MISS.CH2 DRAM_READ_CAS.CH0 DRAM_READ_CAS.AUTOPRE_CH0 DRAM_READ_CAS.CH1 DRAM_READ_CAS.AUTOPRE_CH1 DRAM_READ_CAS.CH2 DRAM_READ_CAS.AUTOPRE_CH2 DRAM_WRITE_CAS.CH0 DRAM_WRITE_CAS.AUTOPRE_CH0 DRAM_WRITE_CAS.CH1 DRAM_WRITE_CAS.AUTOPRE_CH1 DRAM_WRITE_CAS.CH2 DRAM_WRITE_CAS.AUTOPRE_CH2 DRAM_REFRESH.CH0 DRAM_REFRESH.CH1 DRAM_REFRESH.CH2 DRAM_PRE_ALL.CH0 DRAM_PRE_ALL.CH1 DRAM_PRE_ALL.CH2 CB0_XSNP_RESPONSE.RSPIHITI CB0_XSNP_RESPONSE.RSPIHITFSE CB0_XSNP_RESPONSE.RSPSHITFSE CB0_XSNP_RESPONSE.RSPSFWDM CB0_XSNP_RESPONSE.AND_XCORE CB0_XSNP_RESPONSE_AND_XCORE2 CB0_CACHE_LOOKUP.M CB0_CACHE_LOOKUP.E CB0_CACHE_LOOKUP.S CB0_CACHE_LOOKUP.I CB0_CACHE_LOOKUP.AND_READ CB0_CACHE_LOOKUP_AND_READ2 CB0_CACHE_LOOKUP.AND_EXTSNP CB0_CACHE_LOOKUP.AND_ANY IMPH_CB0_TRK_OCCUPANCY.ALL IMPH_CB0_TRK_REQUEST.ALL IMPH_CB0_TRK_REQUEST.WRITES IMPH_C0H_TRK_OCCUPANCY.ALL IMPC_C0H_TRK_REQUEST.ALL GQ_OCCUPANCY.READ_TRACKER GQ_SNOOP.GOTO_S GQ_SNOOP.GOTO_I GQ_SNOOP.GOTO_S_HIT_E GQ_SNOOP.GOTO_S_HIT_F GQ_SNOOP.GOTO_S_HIT_M GQ_SNOOP.GOTO_S_HIT_S GQ_SNOOP.GOTO_I_HIT_E GQ_SNOOP.GOTO_I_HIT_F GQ_SNOOP.GOTO_I_HIT_M GQ_SNOOP.GOTO_I_HIT_S QMC_OCCUPANCY.ANY IMC_RETRY.CH0 IMC_RETRY.CH1 IMC_RETRY.CH2 IMC_RETRY.ANY QHL_FRC_ACK_CNFLTS.IOH QHL_FRC_ACK_CNFLTS.REMOTE QHL_FRC_ACK_CNFLTS.ANY QHL_SLEEPS.IOH_ORDER QHL_SLEEPS.REMOTE_ORDER QHL_SLEEPS.LOCAL_ORDER QHL_SLEEPS.IOH_CONFLICT QHL_SLEEPS.REMOTE_CONFLICT QHL_SLEEPS.LOCAL_CONFLICT ADDR_OPCODE_MATCH.IOH ADDR_OPCODE_MATCH.REMOTE ADDR_OPCODE_MATCH.LOCAL QPI_TX_HEADER.FULL.LINK_0 QPI_TX_HEADER.FULL.LINK_1 DRAM_THERMAL_THROTTLED THERMAL_THROTTLED_TEMP.CORE_0 THERMAL_THROTTLED_TEMP.CORE_1 THERMAL_THROTTLED_TEMP.CORE_2 THERMAL_THROTTLED_TEMP.CORE_3 PROCHOT_ASSERTION TURBO_MODE.CORE_0 TURBO_MODE.CORE_1 TURBO_MODE.CORE_2 TURBO_MODE.CORE_3 CYCLES_UNHALTED_L3_FLL_ENABLE DC_ACCESSES DC_MISSES DC_REFILLS_FROM_L2 DC_REFILLS_FROM_SYSTEM DC_WRITEBACKS L1_DTLB_MISS_AND_L2_DTLB_HITS L1_AND_L2_DTLB_MISSES MISALIGNED_REFERENCES IC_FETCHES IC_MISSES L1_ITLB_MISSES L1_L2_ITLB_MISSES RETIRED_INSTRUCTIONS RETIRED_OPS RETIRED_BRANCHES_MISPREDICTED RETIRED_FAR_CONTROL_TRANSFERS RETIRED_RESYNC_BRANCHES FP_DISPATCHED_FPU_OPS LS_SEGMENT_REGISTER_LOAD LS_BUFFER2_FULL LS_LOCKED_OPERATION LS_RETIRED_CPUID_INSTRUCTIONS DC_ACCESS DC_MISS DC_REFILL_FROM_L2 DC_REFILL_FROM_SYSTEM DC_COPYBACK DC_MISALIGNED_DATA_REFERENCE DC_ONE_BIT_ECC_ERROR DC_DCACHE_ACCESSES_BY_LOCKS BU_CPU_CLK_UNHALTED BU_INTERNAL_L2_REQUEST BU_FILL_REQUEST_L2_MISS BU_FILL_INTO_L2 IC_FETCH IC_REFILL_FROM_L2 IC_REFILL_FROM_SYSTEM IC_INSTRUCTION_FETCH_STALL IC_RETURN_STACK_HIT IC_RETURN_STACK_OVERFLOW FR_RETIRED_X86_INSTRUCTIONS FR_RETIRED_UOPS FR_RETIRED_BRANCHES FR_RETIRED_TAKEN_BRANCHES FR_RETIRED_RESYNCS FR_RETIRED_NEAR_RETURNS FR_RETIRED_FPU_INSTRUCTIONS FR_INTERRUPTS_MASKED_CYCLES FR_TAKEN_HARDWARE_INTERRUPTS FR_DECODER_EMPTY FR_DISPATCH_STALLS FR_FPU_EXCEPTIONS NB_SIZED_COMMANDS NB_PROBE_RESULT NB_HT_BUS0_BANDWIDTH NB_HT_BUS1_BANDWIDTH NB_HT_BUS2_BANDWIDTH TC_DELIVER_MODE BPU_FETCH_REQUEST ITLB_REFERENCE MEMORY_CANCEL MEMORY_COMPLETE LOAD_PORT_REPLAY STORE_PORT_REPLAY MOB_LOAD_REPLAY PAGE_WALK_TYPE BSQ_CACHE_REFERENCE IOQ_ALLOCATION IOQ_ACTIVE_ENTRIES FSB_DATA_ACTIVITY BSQ_ALLOCATION BSQ_ACTIVE_ENTRIES SSE_INPUT_ASSIST PACKED_SP_UOP PACKED_DP_UOP SCALAR_SP_UOP SCALAR_DP_UOP 64BIT_MMX_UOP 128BIT_MMX_UOP X87_FP_UOP X87_SIMD_MOVES_UOP GLOBAL_POWER_EVENTS TC_MS_XFER UOP_QUEUE_WRITES RETIRED_MISPRED_BRANCH_TYPE RETIRED_BRANCH_TYPE RESOURCE_STALL WC_BUFFER B2B_CYCLES BNR RESPONSE FRONT_END_EVENT EXECUTION_EVENT REPLAY_EVENT UOPS_RETIRED UOP_TYPE MISPRED_BRANCH_RETIRED X87_ASSIST MACHINE_CLEAR DATA_READ DATA_WRITE DATA_TLB_MISS DATA_READ_MISS DATA_WRITE_MISS DATA_CACHE_LINES_WRITTEN_BACK EXTERNAL_SNOOPS MEMORY_ACCESSES_IN_BOTH_PIPES BANK_CONFLICTS CODE_READ CODE_TLB_MISS CODE_CACHE_MISS ANY_SEGMENT_REGISTER_LOADED BTB_HITS TAKEN_BRANCH_OR_BTB_HIT PIPELINE_FLUSHES INSTRUCTIONS_EXECUTED_V_PIPE BUS_CYCLE_DURATION LOCKED_BUS_CYCLE IO_READ_OR_WRITE_CYCLE NONCACHEABLE_MEMORY_READS PIPELINE_AGI_STALLS FLOPS DATA_READ_OR_WRITE DATA_READ_MISS_OR_WRITE_MISS BUS_OWNERSHIP_LATENCY BUS_OWNERSHIP_TRANSFERS CACHE_M_LINE_SHARING CACHE_LINE_SHARING EMMS_INSTRUCTIONS_EXECUTED WRITES_TO_NONCACHEABLE_MEMORY SATURATIONS_PERFORMED MMX_INSTRUCTION_DATA_READS MMX_INSTRUCTION_DATA_WRITES PREDICTED_RETURNS MMX_MULTIPLY_UNIT_INTERLOCK BTB_FALSE_ENTRIES DATA_MEM_REFS DCU_LINES_IN DCU_M_LINES_IN DCU_M_LINES_OUT DCU_MISS_OUTSTANDING IFU_FETCH IFU_FETCH_MISS ITLB_MISS IFU_MEM_STALL L2_M_LINES_INM L2_M_LINES_OUTM L2_DBUS_BUSY BUS_REQ_OUTSTANDING BUS_TRAN_BRD BUS_TRAN_RFO BUS_TRAN_IFETCH BUS_TRAN_INVAL BUS_TRAN_PWR BUS_TRAN_DEF BUS_TRAN_BURST BUS_TRAN_ANY BUS_TRAN_MEM BUS_SNOOP_STALL FP_COMPS_OPS_EXE LD_BLOCKS SB_DRAINS MISALIGN_MEM_REF EMON_KNI_PREF_DISPATCHED EMON_KNI_PREF_MISS EMON_KNI_INST_RETIRED EMON_KNI_COMP_INST_RET HW_INT_RX BR_INST_RETIRED BR_MISS_PRED_RETIRED BR_TAKEN_RETIRED BR_MISS_PRED_TAKEN_RET BTB_MISSES BR_BOGUS RESOURCE_STALLS PARTIAL_RAT_STALLS MMX_INSTR_EXEC MMX_SAT_INSTR_EXEC MMX_UOPS_EXEC MMX_INSTR_TYPE_EXEC FP_MMX_TRANS MMX_ASSIST MMX_INSTR_RET SEG_REG_RENAMES RET_SEG_RENAMES EMON_EST_TRANS EMON_THERMAL_TRIP EMON_SIMD_INSTR_RETIRED EMON_SYNCH_UOPS EMON_ESP_UOPS EMON_FUSED_UOPS_RET EMON_UNFUSION EMON_PREF_RQSTS_UP EMON_PREF_RQSTS_DN EMON_SSE_SSE2_INST_RETIRED DATA_DEPENDENCY_STALLED BRANCH_MISPRED DC_FULL_CYCLE DC_FULL_CONTIG DC_WRITEBACK PC_CHANGE BRANCH_RETIRED_ALL INSTR_CYCLE CP_STALL PC_CHANGE_ALL PIPELINE_FLUSH BACKEND_STALL MULTIPLIER_USE MULTIPLIER_STALLED DATA_CACHE_STALLED L2_CACHE_REQ L2_CACHE_MISS SELF_ADDRESS_BUS_TRANS DATA_BUS_TRANS INSTR_EXECUTED BRANCH_COMPLETED RETURN_MISPRED RETURN_NOT_31 RETURN_NOTPRED ITLB_ACCESS DTLB_ACCESS JTLB_IACCESS JTLB_IMISS JTLB_DACCESS JTLB_DMISS DC_LOADSTORE LOAD_MISS INTEGER_COMPLETED FP_COMPLETED LOAD_COMPLETED BARRIER_COMPLETED MIPS16_COMPLETED NOP_COMPLETED INTEGER_MULDIV_COMPLETED RF_STALL INSTR_REFETCH STORE_COND_COMPLETED STORE_COND_FAILED ICACHE_REQUESTS ICACHE_HIT L2_WRITEBACK L2_ACCESS L2_ERR_CORRECTED RF_CYCLES_STALLED IFU_CYCLES_STALLED ALU_CYCLES_STALLED UNCACHED_LOAD UNCACHED_STORE CP2_REG_TO_REG_COMPLETED MFTC_COMPLETED IC_BLOCKED_CYCLES DC_BLOCKED_CYCLES L2_IMISS_STALL_CYCLES L2_DMISS_STALL_CYCLES DMISS_CYCLES L2_MISS_CYCLES UNCACHED_BLOCK_CYCLES MDU_STALL_CYCLES FPU_STALL_CYCLES CP2_STALL_CYCLES COREXTEND_STALL_CYCLES ISPRAM_STALL_CYCLES DSPRAM_STALL_CYCLES CACHE_STALL_CYCLES LOAD_TO_USE_STALLS BASE_MISPRED_STALLS CPO_READ_STALLS BRANCH_MISPRED_CYCLES IFETCH_BUFFER_FULL FETCH_BUFFER_ALLOCATED EJTAG_ITRIGGER EJTAG_DTRIGGER FSB_LT_QUARTER FSB_QUARTER_TO_HALF FSB_GT_HALF FSB_FULL_PIPELINE_STALLS LDQ_LT_QUARTER LDQ_QUARTER_TO_HALF LDQ_GT_HALF LDQ_FULL_PIPELINE_STALLS WBB_LT_QUARTER WBB_QUARTER_TO_HALF WBB_GT_HALF WBB_FULL_PIPELINE_STALLS REQUEST_LATENCY REQUEST_COUNT TLB_BIT_TRANSITIONS PMON_EXCEPT PMON_SIG VPU_INSTR_COMPLETED VFPU_INSTR_COMPLETED VIU1_INSTR_COMPLETED VIU2_INSTR_COMPLETED MTVSCR_INSTR_COMPLETED MTVRSAVE_INSTR_COMPLETED VPU_INSTR_WAIT_CYCLES VFPU_INSTR_WAIT_CYCLES VIU1_INSTR_WAIT_CYCLES VIU2_INSTR_WAIT_CYCLES MFVSCR_SYNC_CYCLES VSCR_SAT_SET STORE_INSTR_COMPLETED L1_INSTR_CACHE_MISSES L1_DATA_SNOOPS UNRESOLVED_BRANCHES SPEC_BUFFER_CYCLES BRANCH_UNIT_STALL_CYCLES TRUE_BRANCH_TARGET_HITS BRANCH_LINK_STAC_PREDICTED GPR_ISSUE_QUEUE_DISPATCHES CYCLES_THREE_INSTR_DISPATCHED CYCLES_NO_COMPLETED_INSTRS BRANCHES_COMPLETED EIEIO_INSTR_COMPLETED MTSPR_INSTR_COMPLETED SC_INSTR_COMPLETED LS_LM_COMPLETED ITLB_HW_TABLE_SEARCH_CYCLES L1_INSTR_CACHE_ACCESSES INSTR_BKPT_MATCHES L1_DATA_SNOOP_HIT_ON_MODIFIED LOAD_MISS_ALIAS LOAD_MISS_ALIAS_ON_TOUCH TOUCH_ALIAS L1_DATA_SNOOP_HIT_CASTOUT L1_DATA_SNOOP_HITS WRITE_THROUGH_STORES CACHE_INHIBITED_STORES L1_DATA_LOAD_HIT L1_DATA_TOUCH_HIT L1_DATA_STORE_HIT L1_DATA_TOTAL_HITS DST_INSTR_DISPATCHED REFRESHED_DSTS SUCCESSFUL_DST_TABLE_SEARCHES DSS_INSTR_COMPLETED VTQ_LINE_FETCH_HIT VEC_LOAD_INSTR_COMPLETED FPU_RENORMALIZATION FPU_DENORMALIZATION FP_STORE_CAUSES_STALL_IN_LSU LD_ST_TRUE_ALIAS_STALL LSU_INDEXED_ALIAS_STALL LSU_ALIAS_VS_FSQ_WB0_WB1 LSU_ALIAS_VS_CSQ LSU_TOUCH_ALIAS_VS_CSQ LSU_LMQ_FULL_STALL LSU_RA_LATCH_STALL LSU_LMQ_INDEX_ALIAS LSU_STORE_QUEUE_INDEX_ALIAS LSU_CSQ_FORWARDING LSU_MISALIGNED_LOAD_FINISH LSU_MISALIGN_STORE_COMPLETED LSU_MISALIGN_STALL FP_ALL_FPSCR_RENAMES_BUSY FP_DENORMALIZED_RESULT L1_DATA_TOTAL_MISSES DISPATCHES_TO_FPR_ISSUE_QUEUE LSU_INSTR_COMPLETED SS_SM_INSTR_COMPLETED TLBIE_INSTR_COMPLETED LWARX_INSTR_COMPLETED MFSPR_INSTR_COMPLETED REFETCH_SERIALIZATION CYCLES_ONE_INSTR_DISPATCHED CYCLES_TWO_INSTR_COMPLETED ITLB_NON_SPECULATIVE_MISSES L1_DATA_LOAD_ACCESS_MISS L1_DATA_TOUCH_MISS L1_DATA_STORE_MISS L1_DATA_TOUCH_MISS_CYCLES L1_DATA_CYCLES_USED VTQ_RESUMES_DUE_TO_CTX_CHANGE VTQ_LINE_FETCH_MISS VTQ_LINE_FETCH TLBIE_SNOOPS L1_INSTR_CACHE_RELOADS L1_DATA_CACHE_RELOADS L1_DATA_CACHE_CASTOUTS_TO_L2 STORE_MERGE_GATHER DATA_BKPT_MATCHES BPU_STALL_ON_LR_DEPENDENCY BTIC_MISS FPR_ISSUE_STALLED SWITCHES_BETWEEN_PRIV_USER LSU_COMPLETES_FP_STORE_SINGLE VR_ISSUE_QUEUE_DISPATCHES VR_STALLS FPR_ISSUE_QUEUE_ENTRIES STWCX_INSTR_COMPLETED LS_LM_INSTR_PIECES L1_DATA_CACHE_OP_HIT L1_DATA_LOAD_MISS_CYCLES L1_DATA_PUSHES L1_DATA_TOTAL_MISS VT2_FETCHES TAKEN_BRANCHES_PROCESSED BRANCH_FLUSHES FAST_BTIC_HIT CYCLES_THREE_INSTR_COMPLETED CYCLES_NO_INSTR_DISPATCHED GPR_ISSUE_QUEUE_STALLED DSSALL_INSTR_COMPLETED TLBSYNC_INSTR_COMPLETED SS_SM_INSTR_PIECES DTLB_HW_SEARCH_CYCLES SNOOP_RETRIES SUCCESSFUL_STWCX MISPREDICTED_BRANCHES FOLDED_BRANCHES L2_CACHE_HITS L3_CACHE_HITS L2_INSTR_CACHE_MISSES L3_INSTR_CACHE_MISSES L2_DATA_CACHE_MISSES L3_DATA_CACHE_MISSES L2_LOAD_HITS L2_STORE_HITS L3_LOAD_HITS L3_STORE_HITS L2_TOUCH_HITS L3_TOUCH_HITS SNOOP_MODIFIED SNOOP_VALID INTERVENTION L2_CACHE_MISSES L3_CACHE_MISSES L2_CACHE_CASTOUTS L3_CACHE_CASTOUTS L2SQ_FULL_CYCLES L3SQ_FULL_CYCLES RAQ_FULL_CYCLES WAQ_FULL_CYCLES L1_EXTERNAL_INTERVENTIONS L2_EXTERNAL_INTERVENTIONS L3_EXTERNAL_INTERVENTIONS EXTERNAL_PUSHES EXTERNAL_SNOOP_RETRY DTQ_FULL_CYCLES BUS_RETRY L2_VALID_REQUEST BORDQ_FULL BUS_TAS_FOR_READS BUS_TAS_FOR_WRITES BUS_READS_NOT_RETRIED BUS_WRITES_NOT_RETRIED BUS_READS_WRITES_NOT_RETRIED BUS_RETRY_DUE_TO_L1_RETRY BUS_RETRY_DUE_TO_COLLISION SNOOP_REQUESTS PREFETCH_ENGINE_REQUEST PREFETCH_ENGINE_FULL TSC STANDALONE AMD_K7 AMD_K8 INTEL_P5 INTEL_P6 INTEL_CL INTEL_PII INTEL_PIII INTEL_PM INTEL_PIV INTEL_CORE INTEL_CORE2 INTEL_CORE2EXTREME INTEL_ATOM INTEL_COREI7 INTEL_WESTMERE INTEL_SANDYBRIDGE INTEL_XSCALE MIPS_24K PPC_7450 GENERIC P4 IAF IAP UCF UCP MIPS24K PPC7450 SOFT INTERRUPT EDGE THRESHOLD INVERT QUALIFIER PRECISE TAGGING CASCADE SOFT- TSC- k7-retired-branches branch-mispredicts k7-dc-misses k7-ic-misses k7-retired-instructions k7-hardware-interrupts K7- p5-taken-branches p5-code-cache-miss p5-instructions-executed p5-hardware-interrupts unhalted-cycles P5- p6-br-inst-retired p6-br-miss-pred-retired p6-dcu-lines-in p6-ifu-fetch-miss p6-inst-retired p6-hw-int-rx p6-cpu-clk-unhalted P6- k8-fr-retired-taken-branches k8-dc-miss k8-ic-miss k8-bu-cpu-clk-unhalted K8- iap-br-inst-retired.any iap-br-inst-retired.mispred tsc-tsc iap-l1i-misses iaf-instr-retired.any iap-hw-int-rcv iaf-cpu-clk-unhalted.core IAF- iap-inst-retired.any_p iap-cpu-clk-unhalted.core_p IAP- iap-br-instr-ret iap-br-mispred-ret iap-icache-misses iap-instr-ret iap-core-hw-int-rx iap-unhalted-core-cycles UCF- UCP- p4-mispred-branch-retired p4-global-power-events P4- SOFT-CLOCK.HARD dd db di bd bb bi ib tcmiss hit-uc st-rb-full 64k-conf lsc ssc split-ld split-st no-sta no-std partial-data unalgn-addr dtmiss itmiss rd-2ndl-hits rd-2ndl-hite rd-2ndl-hitm rd-3rdl-hits rd-3rdl-hite rd-3rdl-hitm rd-2ndl-miss rd-3rdl-miss wr-2ndl-miss all-read all-write mem-uc mem-wc mem-wt mem-wp mem-wb prefetch drdy-drv drdy-own drdy-other dbsy-drv dbsy-own dbsy-other req-type0 req-type1 req-len0 req-len1 req-io-type req-lock-type req-cache-type req-split-type req-dem-type req-ord-type mem-type0 mem-type1 mem-type2 allp0 allp2 running cisc from-tc-build from-tc-deliver from-rom conditional call return indirect sbfull wcb-evicts wcb-full-evict nbogus nbogus0 nbogus1 nbogus2 nbogus3 nbogusntag nbogustag tagloads tagstores mmnp mmnm mmtp mmtm fpsu fpso poao poau prea moclear smclear this only exclude frequency clean cmp2s cmp2i DMND_DATA_RD DMND_RFO DMND_IFETCH PF_DATA_RD PF_RFO PF_IFETCH UNCORE_HIT OTHER_CORE_HIT_SNP OTHER_CORE_HITM REMOTE_CACHE_FWD REMOTE_DRAM NON_DRAM add-pipe-excluding-junk-ops store-pipe-excluding-junk-ops add-pipe-junk-ops multiply-pipe-junk-ops store-pipe-junk-ops cs fs gs hs locked-instructions cycles-in-request cycles-to-complete invalid shared exclusive owner modified scrubber piggyback store nta accesses ic-fill dc-fill tlb-reload tag-snoop cancelled dirty-l2-victim victim-from-l2 x87 mmx-3dnow packed-sse-sse2 scalar-sse-sse2 low-op-pos-0 low-op-pos-1 low-op-pos-2 x87-reclass-microfaults sse-retype-microfaults sse-reclass-microfaults sse-and-x87-microtraps page-hit page-miss page-conflict dimm-turnaround read-to-write-turnaround write-to-read-turnaround dram-controller-queue-bypass nonpostwrszbyte nonpostwrszdword rdszbyte rdszdword rdmodwr probe-miss probe-hit command buffer-release nop self t1 t2 wos packed-and-scalar packed-multiply packed-shift unpack packed-logical packed-arithmetic mmxtofp fptommx freq loadop stdsta sse-packed-single sse2-packed-double sse2-scalar-double sse-scalar-single nonhw BR_INST_RETIRED.MISPRED_NOT_TAKEN BR_INST_RETIRED.PRED_NOT_TAKEN CYCLES_INT_MASKED.CYCLES_INT_MASKED CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED SIMD_COMP_INST_RETIRED.PACKED_DOUBLE SIMD_COMP_INST_RETIRED.PACKED_SINGLE SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE SIMD_COMP_INST_RETIRED.SCALAR_SINGLE SIMD_INST_RETIRED.PACKED_DOUBLE SIMD_INST_RETIRED.PACKED_SINGLE SIMD_INST_RETIRED.SCALAR_DOUBLE SIMD_INST_RETIRED.SCALAR_SINGLE SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR SIMD_UOP_TYPE_EXEC.ARITHMETIC.S MEM_LOAD_RETIRED.L1D_LINE_MISS RAT_STALLS.OTHER_SERIALIZATION_STALLS DTLB_LOAD_MISSES.WALK_COMPLETED DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT MEM_UNCORE_RETIRED.REMOTE_DRAM MEM_UNCORE_RETIRED.UNCACHEABLE FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION L2_DATA_RQSTS.PREFETCH.I_STATE L2_DATA_RQSTS.PREFETCH.S_STATE L2_DATA_RQSTS.PREFETCH.E_STATE L2_DATA_RQSTS.PREFETCH.M_STATE DTLB_MISSES.LARGE_WALK_COMPLETED L1D_CACHE_PREFETCH_LOCK_FB_HIT BR_INST_EXEC.INDIRECT_NON_CALL BR_INST_EXEC.INDIRECT_NEAR_CALL BR_MISP_EXEC.INDIRECT_NON_CALL BR_MISP_EXEC.INDIRECT_NEAR_CALL OFFCORE_REQUESTS.L1D_WRITEBACK UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 UOPS_EXECUTED.CORE_ACTIVE_CYCLES SSEX_UOPS_RETIRED.PACKED_SINGLE SSEX_UOPS_RETIRED.SCALAR_SINGLE SSEX_UOPS_RETIRED.PACKED_DOUBLE SSEX_UOPS_RETIRED.SCALAR_DOUBLE SSEX_UOPS_RETIRED.VECTOR_INTEGER MEM_LOAD_RETIRED.L3_UNSHARED_HIT MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM MEMORY_DISAMBIGURATION.SUCCESS MEMORY_DISAMBIGURATION.WATCHDOG MEMORY_DISAMBIGURATION.WATCH_CYCLES HW_INT.CYCLES_PENDING_AND_MASKED L1D_PEND_MISS.LOAD_BUFFERS_FULL OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO OFFCORE_REQUESTS_OUTSTANDING.ANY.READ ITLB_MISSES.LARGE_WALK_COMPLETED OFFCORE_REQUESTS.DEMAND.READ_DATA OFFCORE_REQUESTS.DEMAND.READ_CODE SNOOPQ_REQUESTS_OUTSTANDING.DATA SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE SNOOPQ_REQUESTS_OUTSTANDING.CODE LD_BLOCKS_PARTIAL.ADDRESS_ALIAS LD_BLOCKS_PARTIAL.ALL_STA_BLOCK DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK DTLB_LOAD_MISSES.WALK_DURATION FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE FP_COMP_OPS_EXE.SSE_PACKED_SINGLE FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE CPU_CLK_THREAD_UNHALTED.REF_XCLK DTLB_STORE_MISSES.MISS_CAUSES_A_WALK DTLB_STORE_MISSES.WALK_COMPLETED DTLB_STORE_MISSES.WALK_DURATION PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW PARTIAL_RAT_STALLS.MUL_SINGLE_UOP RESOURCE_STALLS2.ALL_PRF_CONTROL OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION LOCK_CYCLES.CACHE_LOCK_DURATION ITLB_MISSES.MISS_CAUSES_A_WALK BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET UOPS_DISPATCHED_PORT.PORT_2_LD UOPS_DISPATCHED_PORT.PORT_2_STA UOPS_DISPATCHED_PORT.PORT_3_LD UOPS_DISPATCHED_PORT.PORT_3_STA DSB2MITE_SWITCHES.PENALTY_CYCLES OFFCORE_REQUESTS.DEMAND_DATA_RD OFFCORE_REQUESTS_BUFFER.SQ_FULL L1D_BLOCKS.BANK_CONFLICT_CYCLES OTHER_ASSISTS.ITLB_MISS_RETIRED MACHINE_CLEARS.MEMORY_ORDERING MEM_TRANS_RETIRED.LOAD_LATENCY MEM_TRANS_RETIRED.PRECISE_STORE MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT GQ_CYCLES_FULL.PEER_PROBE_TRACKER GQ_CYCLES_NOT_EMPTY.READ_TRACKER GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER SNP_RESP_TO_LOCAL_HOME.I_STATE SNP_RESP_TO_LOCAL_HOME.S_STATE SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE SNP_RESP_TO_LOCAL_HOME.CONFLICT SNP_RESP_TO_REMOTE_HOME.I_STATE SNP_RESP_TO_REMOTE_HOME.S_STATE SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE SNP_RESP_TO_REMOTE_HOME.CONFLICT QMC_CRITICAL_PRIORITY_READS.CH0 QMC_CRITICAL_PRIORITY_READS.CH1 QMC_CRITICAL_PRIORITY_READS.CH2 QMC_CRITICAL_PRIORITY_READS.ANY QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0 QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0 QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0 QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1 QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1 QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1 QPI_TX_STALLED_SINGLE_FLIT.LINK_0 QPI_TX_STALLED_SINGLE_FLIT.LINK_1 QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0 QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0 QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0 QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1 QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1 QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1 QPI_TX_STALLED_MULTI_FLIT.LINK_0 QPI_TX_STALLED_MULTI_FLIT.LINK_1 QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0 QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1 CB0_XSNP_RESPONSE.AND_EXTERNAL IMPH_CB0_TRK_REQUEST.EVICTIONS THERMAL_THROTTLING_TEMP.CORE_0 THERMAL_THROTTLING_TEMP.CORE_1 THERMAL_THROTTLING_TEMP.CORE_2 THERMAL_THROTTLING_TEMP.CORE_3 THERMAL_THROTTLING_PROCHOT.CORE_0 THERMAL_THROTTLING_PROCHOT.CORE_1 THERMAL_THROTTLING_PROCHOT.CORE_2 THERMAL_THROTTLING_PROCHOT.CORE_3 CYCLES_UNHALTED_L3_FLL_DISABLE RETIRED_TAKEN_BRANCHES_MISPREDICTED INTERRUPTS_MASKED_WHILE_PENDING_CYCLES FP_CYCLES_WITH_NO_FPU_OPS_RETIRED FP_DISPATCHED_FPU_FAST_FLAG_OPS LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP LS_MICROARCHITECTURAL_LATE_CANCEL LS_RETIRED_CFLUSH_INSTRUCTIONS DC_L1_DTLB_MISS_AND_L2_DTLB_HIT DC_L1_DTLB_MISS_AND_L2_DTLB_MISS DC_MICROARCHITECTURAL_LATE_CANCEL DC_MICROARCHITECTURAL_EARLY_CANCEL DC_DISPATCHED_PREFETCH_INSTRUCTIONS IC_L1_ITLB_MISS_AND_L2_ITLB_HIT IC_L1_ITLB_MISS_AND_L2_ITLB_MISS IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP FR_RETIRED_BRANCHES_MISPREDICTED FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED FR_RETIRED_FAR_CONTROL_TRANSFERS FR_RETIRED_NEAR_RETURNS_MISPREDICTED FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE FR_DISPATCH_STALL_FOR_SERIALIZATION FR_DISPATCH_STALL_FOR_SEGMENT_LOAD FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL FR_DISPATCH_STALL_WHEN_FPU_IS_FULL FR_DISPATCH_STALL_WHEN_LS_IS_FULL FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING FR_NUMBER_OF_BREAKPOINTS_FOR_DR0 FR_NUMBER_OF_BREAKPOINTS_FOR_DR1 FR_NUMBER_OF_BREAKPOINTS_FOR_DR2 FR_NUMBER_OF_BREAKPOINTS_FOR_DR3 NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED NB_MEMORY_CONTROLLER_TURNAROUND NB_MEMORY_CONTROLLER_BYPASS_SATURATION WRITE_HIT_TO_M_OR_E_STATE_LINES EXTERNAL_DATA_CACHE_SNOOP_HITS MISALIGNED_DATA_OR_IO_REFERENCES WRITE_BUFFER_FULL_STALL_DURATION WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE BREAKPOINT_MATCH_ON_DR0_REGISTER BREAKPOINT_MATCH_ON_DR1_REGISTER BREAKPOINT_MATCH_ON_DR2_REGISTER BREAKPOINT_MATCH_ON_DR3_REGISTER MMX_INSTRUCTIONS_EXECUTED_U_PIPE MMX_INSTRUCTIONS_EXECUTED_V_PIPE TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY SATURATING_MMX_INSTRUCTIONS_EXECUTED NUMBER_OF_CYCLES_NOT_IN_HALT_STATE DATA_CACHE_TLB_MISS_STALL_DURATION MMX_INSTRUCTION_DATA_READ_MISSES FLOATING_POINT_STALLS_DURATION D1_STARVATION_AND_FIFO_IS_EMPTY D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO MMX_INSTRUCTION_DATA_WRITE_MISSES PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS MISPREDICTED_OR_UNPREDICTED_RETURNS MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE EMON_SSE_SSE2_COMP_INST_RETIRED THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD L1_DATA_SNOOP_HIT_CASTOUT_QUEUE DST_STREAM_0_CACHE_LINE_FETCHES VTQ_SUSPENDS_DUE_TO_CTX_CHANGE FP_STORE_INSTR_COMPLETED_IN_LSU LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0 LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0 LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1 FP_LOAD_INSTR_COMPLETED_IN_LSU FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU FP_LOAD_DOUBLE_COMPLETED_IN_LSU LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL FP_ONE_QUARTER_FPSCR_RENAMES_BUSY FP_ONE_HALF_FPSCR_RENAMES_BUSY FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS DST_STREAM_1_CACHE_LINE_FETCHES VTQ_STREAM_CANCELED_PREMATURELY CACHEABLE_STORE_MERGE_TO_32_BYTES FALL_THROUGH_BRANCHES_PROCESSED FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY SECOND_SPECULATION_BUFFER_ACTIVE BRANCH_LINK_STACK_CORRECTLY_RESOLVED GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD CANCELLED_L1_INSTR_CACHE_MISSES SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY THIRD_SPECULATION_BUFFER_ACTIVE BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY BRANCH_LINK_STACK_MISPREDICTED GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD DST_STREAM_3_CACHE_LINE_FETCHES THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY FP_STORE_DOUBLE_COMPLETES_IN_LSU BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT BUS_RETRY_DUE_TO_INTERVENTION_ORDERING PREFETCH_ENGINE_COLLISION_VS_LOAD PREFETCH_ENGINE_COLLISION_VS_STORE PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH k7-retired-branches-mispredicted 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* * S &* 9* * L* &* 9* % & ^* a* 0 ^* a* 0 $FreeBSD: release/9.1.0/lib/csu/i386-elf/crti.S 217105 2011-01-07 16:07:51Z kib $ GCC: (GNU) 4.2.1 20070831 patched [FreeBSD] $FreeBSD: release/9.1.0/lib/libpmc/pmclog.c 236238 2012-05-29 14:50:21Z fabient $ GCC: (GNU) 4.2.1 20070831 patched [FreeBSD] $FreeBSD: release/9.1.0/lib/libpmc/libpmc.c 236238 2012-05-29 14:50:21Z fabient $ GCC: (GNU) 4.2.1 20070831 patched [FreeBSD] GCC: (GNU) 4.2.1 20070831 patched [FreeBSD] GCC: (GNU) 4.2.1 20070831 patched [FreeBSD] $FreeBSD: release/9.1.0/lib/csu/i386-elf/crtn.S 217105 2011-01-07 16:07:51Z kib $ .shstrtab .hash .dynsym .dynstr .gnu.version .gnu.version_r .rel.dyn .rel.plt .init .text .fini .rodata .eh_frame .ctors .dtors .jcr .data.rel.ro .dynamic .got .got.plt .data .bss .comment 0 p T T m ! o
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