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NTUOPS_RETIREDUOP_TYPEMISPRED_BRANCH_RETIREDX87_ASSISTMACHINE_CLEARDATA_READDATA_WRITEDATA_TLB_MISSDATA_READ_MISSDATA_WRITE_MISSDATA_CACHE_LINES_WRITTEN_BACKEXTERNAL_SNOOPSMEMORY_ACCESSES_IN_BOTH_PIPESBANK_CONFLICTSCODE_READCODE_TLB_MISSCODE_CACHE_MISSANY_SEGMENT_REGISTER_LOADEDBTB_HITSTAKEN_BRANCH_OR_BTB_HITPIPELINE_FLUSHESINSTRUCTIONS_EXECUTED_V_PIPEBUS_CYCLE_DURATIONLOCKED_BUS_CYCLEIO_READ_OR_WRITE_CYCLENONCACHEABLE_MEMORY_READSPIPELINE_AGI_STALLSFLOPSDATA_READ_OR_WRITEDATA_READ_MISS_OR_WRITE_MISSBUS_OWNERSHIP_LATENCYBUS_OWNERSHIP_TRANSFERSCACHE_M_LINE_SHARINGCACHE_LINE_SHARINGEMMS_INSTRUCTIONS_EXECUTEDWRITES_TO_NONCACHEABLE_MEMORYSATURATIONS_PERFORMEDMMX_INSTRUCTION_DATA_READSMMX_INSTRUCTION_DATA_WRITESPREDICTED_RETURNSMMX_MULTIPLY_UNIT_INTERLOCKBTB_FALSE_ENTRIESDATA_MEM_REFSDCU_LINES_INDCU_M_LINES_INDCU_M_LINES_OUTDCU_MISS_OUTSTANDINGIFU_FETCHIFU_FETCH_MISSITLB_MISSIFU_MEM_STALLL2_M_LINES_INML2_M_LINES_OUTML2_DBUS_BUSYBUS_REQ_OUTSTANDINGBUS_TRAN_BRDBUS_TRAN_RFOBUS_TRAN_IFETCHBUS_TRAN_INVALBUS_TRAN_PWRBUS_TRAN_DEFBUS_TRAN_BURSTBUS_TRAN_ANYBUS_TRAN_MEMBUS_SNOOP_STALLFP_COMPS_OPS_EXELD_BLOCKSSB_DRAINSMISALIGN_MEM_REFEMON_KNI_PREF_DISPATCHEDEMON_KNI_PREF_MISSEMON_KNI_INST_RETIREDEMON_KNI_COMP_INST_RETHW_INT_RXBR_INST_RETIREDBR_MISS_PRED_RETIREDBR_TAKEN_RETIREDBR_MISS_PRED_TAKEN_RETBTB_MISSESBR_BOGUSRESOURCE_STALLSPARTIAL_RAT_STALLSMMX_INSTR_EXECMMX_SAT_INSTR_EXECMMX_UOPS_EXECMMX_INSTR_TYPE_EXECFP_MMX_TRANSMMX_ASSISTMMX_INSTR_RETSEG_REG_RENAMESRET_SEG_RENAMESEMON_EST_TRANSEMON_THERMAL_TRIPEMON_SIMD_INSTR_RETIREDEMON_SYNCH_UOPSEMON_ESP_UOPSEMON_FUSED_UOPS_RETEMON_UNFUSIONEMON_PREF_RQSTS_UPEMON_PREF_RQSTS_DNEMON_SSE_SSE2_INST_RETIREDDATA_DEPENDENCY_STALLEDBRANCH_MISPREDDC_FULL_CYCLEDC_FULL_CONTIGDC_WRITEBACKPC_CHANGEBRANCH_RETIRED_ALLINSTR_CYCLECP_STALLPC_CHANGE_ALLPIPELINE_FLUSHBACKEND_STALLMULTIPLIER_USEMULTIPLIER_STALLEDDATA_CACHE_STALLEDL2_CACHE_REQL2_CACHE_MISSSELF_ADDRESS_BUS_TRANSDATA_BUS_TRANSINSTR_EXECUTEDBRANCH_COMPLETEDRETURN_MISPREDRETURN_NOT_31RETURN_NOTPREDITLB_ACCESSDTLB_ACCESSJTLB_IACCESSJTLB_IMISSJTLB_DACCESSJTLB_DMISSDC_LOADSTORELOAD_MISSINTEGER_COMPLETEDFP_COMPLETEDLOAD_COMPLETEDBARRIER_COMPLETEDMIPS16_COMPLETEDNOP_COMPLETEDINTEGER_MULDIV_COMPLETEDRF_STALLINSTR_REFETCHSTORE_COND_COMPLETEDSTORE_COND_FAILEDICACHE_REQUESTSICACHE_HITL2_WRITEBACKL2_ACCESSL2_ERR_CORRECTEDRF_CYCLES_STALLEDIFU_CYCLES_STALLEDALU_CYCLES_STALLEDUNCACHED_LOADUNCACHED_STORECP2_REG_TO_REG_COMPLETEDMFTC_COMPLETEDIC_BLOCKED_CYCLESDC_BLOCKED_CYCLESL2_IMISS_STALL_CYCLESL2_DMISS_STALL_CYCLESDMISS_CYCLESL2_MISS_CYCLESUNCACHED_BLOCK_CYCLESMDU_STALL_CYCLESFPU_STALL_CYCLESCP2_STALL_CYCLESCOREXTEND_STALL_CYCLESISPRAM_STALL_CYCLESDSPRAM_STALL_CYCLESCACHE_STALL_CYCLESLOAD_TO_USE_STALLSBASE_MISPRED_STALLSCPO_READ_STALLSBRANCH_MISPRED_CYCLESIFETCH_BUFFER_FULLFETCH_BUFFER_ALLOCATEDEJTAG_ITRIGGEREJTAG_DTRIGGERFSB_LT_QUARTERFSB_QUARTER_TO_HALFFSB_GT_HALFFSB_FULL_PIPELINE_STALLSLDQ_LT_QUARTERLDQ_QUARTER_TO_HALFLDQ_GT_HALFLDQ_FULL_PIPELINE_STALLSWBB_LT_QUARTERWBB_QUARTER_TO_HALFWBB_GT_HALFWBB_FULL_PIPELINE_STALLSREQUEST_LATENCYREQUEST_COUNTTLB_BIT_TRANSITIONSPMON_EXCEPTPMON_SIGVPU_INSTR_COMPLETEDVFPU_INSTR_COMPLETEDVIU1_INSTR_COMPLETEDVIU2_INSTR_COMPLETEDMTVSCR_INSTR_COMPLETEDMTVRSAVE_INSTR_COMPLETEDVPU_INSTR_WAIT_CYCLESVFPU_INSTR_WAIT_CYCLESVIU1_INSTR_WAIT_CYCLESVIU2_INSTR_WAIT_CYCLESMFVSCR_SYNC_CYCLESVSCR_SAT_SETSTORE_INSTR_COMPLETEDL1_INSTR_CACHE_MISSESL1_DATA_SNOOPSUNRESOLVED_BRANCHESSPEC_BUFFER_CYCLESBRANCH_UNIT_STALL_CYCLESTRUE_BRANCH_TARGET_HITSBRANCH_LINK_STAC_PREDICTEDGPR_ISSUE_QUEUE_DISPATCHESCYCLES_THREE_INSTR_DISPATCHEDCYCLES_NO_COMPLETED_INSTRSBRANCHES_COMPLETEDEIEIO_INSTR_COMPLETEDMTSPR_INSTR_COMPLETEDSC_INSTR_COMPLETEDLS_LM_COMPLETEDITLB_HW_TABLE_SEARCH_CYCLESL1_INSTR_CACHE_ACCESSESINSTR_BKPT_MATCHESL1_DATA_SNOOP_HIT_ON_MODIFIEDLOAD_MISS_ALIASLOAD_MISS_ALIAS_ON_TOUCHTOUCH_ALIASL1_DATA_SNOOP_HIT_CASTOUTL1_DATA_SNOOP_HITSWRITE_THROUGH_STORESCACHE_INHIBITED_STORESL1_DATA_LOAD_HITL1_DATA_TOUCH_HITL1_DATA_STORE_HITL1_DATA_TOTAL_HITSDST_INSTR_DISPATCHEDREFRESHED_DSTSSUCCESSFUL_DST_TABLE_SEARCHESDSS_INSTR_COMPLETEDVTQ_LINE_FETCH_HITVEC_LOAD_INSTR_COMPLETEDFPU_RENORMALIZATIONFPU_DENORMALIZATIONFP_STORE_CAUSES_STALL_IN_LSULD_ST_TRUE_ALIAS_STALLLSU_INDEXED_ALIAS_STALLLSU_ALIAS_VS_FSQ_WB0_WB1LSU_ALIAS_VS_CSQLSU_TOUCH_ALIAS_VS_CSQLSU_LMQ_FULL_STALLLSU_RA_LATCH_STALLLSU_LMQ_INDEX_ALIASLSU_STORE_QUEUE_INDEX_ALIASLSU_CSQ_FORWARDINGLSU_MISALIGNED_LOAD_FINISHLSU_MISALIGN_STORE_COMPLETEDLSU_MISALIGN_STALLFP_ALL_FPSCR_RENAMES_BUSYFP_DENORMALIZED_RESULTL1_DATA_TOTAL_MISSESDISPATCHES_TO_FPR_ISSUE_QUEUELSU_INSTR_COMPLETEDSS_SM_INSTR_COMPLETEDTLBIE_INSTR_COMPLETEDLWARX_INSTR_COMPLETEDMFSPR_INSTR_COMPLETEDREFETCH_SERIALIZATIONCYCLES_ONE_INSTR_DISPATCHEDCYCLES_TWO_INSTR_COMPLETEDITLB_NON_SPECULATIVE_MISSESL1_DATA_LOAD_ACCESS_MISSL1_DATA_TOUCH_MISSL1_DATA_STORE_MISSL1_DATA_TOUCH_MISS_CYCLESL1_DATA_CYCLES_USEDVTQ_RESUMES_DUE_TO_CTX_CHANGEVTQ_LINE_FETCH_MISSVTQ_LINE_FETCHTLBIE_SNOOPSL1_INSTR_CACHE_RELOADSL1_DATA_CACHE_RELOADSL1_DATA_CACHE_CASTOUTS_TO_L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