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Current Path : /sys/amd64/compile/hs32/modules/usr/src/sys/modules/mvs/@/amd64/compile/hs32/modules/usr/src/sys/modules/drm/radeon/

FreeBSD hs32.drive.ne.jp 9.1-RELEASE FreeBSD 9.1-RELEASE #1: Wed Jan 14 12:18:08 JST 2015 root@hs32.drive.ne.jp:/sys/amd64/compile/hs32 amd64
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f;f}.tj<tjfI=<mJG=28Y?/>:Z}x~)}X5t}suI=<G=28Y?/>:Z}x~.}X7t~f<,}Jt6tJ=U=28Y[c/>:Z}x}~.~~tX|X=X=28Y[/>:Z}x~F&}Xt .k-Bt>tB=U=28Y[c/>:Z}x}~1"I/)."I/k)~t|X<=u[/>:Z}x~$}Xt .uX|X/X=28Y[c/>:Z}x}~.~k<?WY.R/.;kt;~X&>~$-$zp$fGwyk$p$zts$z$kg$->B$9$jtx}t~/~$~$9G$j+j/~&x}~=~$X$f$2}$x}~K~$}$x}~=~$~$~$~*$$FreeBSD: release/9.1.0/sys/dev/drm/radeon_state.c 229732 2012-01-06 21:16:51Z dim $$FreeBSD: release/9.1.0/sys/dev/drm/drmP.h 215367 2010-11-16 03:43:06Z nwhitehorn $$FreeBSD: release/9.1.0/sys/dev/drm/drm.h 183573 2008-10-03 16:59:11Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/drm_atomic.h 183573 2008-10-03 16:59:11Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/drm_internal.h 182080 2008-08-23 20:59:12Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/drm_linux_list.h 203287 2010-01-31 14:25:29Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/drm.h 183573 2008-10-03 16:59:11Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/drm_sarea.h 182080 2008-08-23 20:59:12Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/drm.h 183573 2008-10-03 16:59:11Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/radeon_drm.h 196471 2009-08-23 15:02:58Z rnoland $$FreeBSD: release/9.1.0/sys/dev/drm/radeon_drv.h 197605 2009-09-28 22:40:29Z rnoland $GCC: (GNU) 4.2.1 20070831 patched [FreeBSD]radeon_cp_setparamradeon_cp_flipradeon_cp_flipradeon_do_init_pageflipradeon_cp_dispatch_flipradeon_clear_boxradeon_cp_getparamradeon_cp_cmdbufradeon_cp_cmdbuf8HX|L@!&T@lDHT""// /0/@/P/`/p/h".  0""", ,@,`,,,--0-H-`-x- P"-,`&@!!H&T",-8,-X,4-x,L-,d-,|-2"$(,,/ / ., ,@,`,,,"radeon_emit_packetsradeon_check_and_fixup_packetsradeon_check_and_fixup_offsetradeon_emit_scalarsradeon_emit_vectorsradeon_emit_packet3radeon_check_and_fixup_packet3radeon_emit_packet3_cliprectradeon_emit_clip_rectradeon_emit_scalars2radeon_emit_waitradeon_emit_veclinearradeon_cp_vertex2radeon_cp_vertex2radeon_emit_state2radeon_emit_stateradeon_cp_dispatch_indicesradeon_cp_dispatch_indirectradeon_cp_dispatch_vertexradeon_cp_textureradeon_cp_textureradeon_cp_dispatch_textureradeon_cp_indirectradeon_cp_indirectradeon_cp_stippleradeon_cp_stippleradeon_cp_dispatch_stippleradeon_cp_indicesradeon_cp_indicesradeon_cp_vertexradeon_cp_vertexradeon_cp_clearradeon_cp_clearradeon_cp_dispatch_clearradeon_cp_swapradeon_cp_swapradeon_cp_dispatch_swapradeon_driver_openradeon_cp_discard_buffer[drm:pid%d:%s] buf=%d s=0x%x e=0x%x
error: [drm:pid%d:%s] *ERROR* ADVANCE_RING(): mismatch: nr: %x write: %x line: %d
[drm:pid%d:%s] pfCurrentPage=%d
[drm:pid%d:%s] color tiling disabled
[drm:pid%d:%s] color tiling enabled
[drm:pid%d:%s] Invalid parameter %d
error: [drm:pid%d:%s] *ERROR* copy_to_user
error: [drm:pid%d:%s] *ERROR* %s called without lock held
error: [drm:pid%d:%s] *ERROR* called with no initialization
[drm:pid%d:%s] idx=%d s=%d e=%d d=%d
error: [drm:pid%d:%s] *ERROR* buffer index %d (of %d max)
error: [drm:pid%d:%s] *ERROR* process %d using buffer owned by %p
error: [drm:pid%d:%s] *ERROR* sending pending buffer %d
error: [drm:pid%d:%s] *ERROR* reusing indirect: start=0x%x actual=0x%x
[drm:pid%d:%s] hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d
error: [drm:pid%d:%s] *ERROR* bad prim %x count %d
error: [drm:pid%d:%s] *ERROR* buffer prim %d
[drm:pid%d:%s]    box:  x1=%d y1=%d  x2=%d y2=%d
[drm:pid%d:%s] hwprim 0x%x vfmt 0x%x %d..%d %d verts
error: [drm:pid%d:%s] *ERROR* bad prim %x numverts %d
[drm:pid%d:%s] %d,%d-%d,%d flags 0x%x
error: [drm:pid%d:%s] *ERROR* null texture image!
[drm:pid%d:%s] offset fixed up to 0x%x
error: [drm:pid%d:%s] *ERROR* Invalid destination offset
error: [drm:pid%d:%s] *ERROR* invalid texture format %d
[drm:pid%d:%s] tex=%dx%d blit=%d
[drm:pid%d:%s] tex: ofs=0x%x p=%d f=%d x=%d y=%d w=%d h=%d
error: [drm:pid%d:%s] *ERROR* EFAULT on pad, %d bytes
error: [drm:pid%d:%s] *ERROR* Invalid final destination offset
error: [drm:pid%d:%s] *ERROR* Invalid depth buffer offset
error: [drm:pid%d:%s] *ERROR* Invalid texture offset for unit 0
error: [drm:pid%d:%s] *ERROR* Invalid texture offset for unit 1
error: [drm:pid%d:%s] *ERROR* Invalid texture offset for unit 2
[drm:pid%d:%s] pid=%d index=%d start=%d end=%d discard=%d
error: [drm:pid%d:%s] *ERROR* misaligned buffer 0x%x
error: [drm:pid%d:%s] *ERROR* no header 0x%x - 0x%x
error: [drm:pid%d:%s] *ERROR* radeon_emit_state failed
[drm:pid%d:%s] pid=%d index=%d count=%d discard=%d
[drm:pid%d:%s] pid=%d index=%d discard=%d
error: [drm:pid%d:%s] *ERROR* radeon_emit_state2 failed
[drm:pid%d:%s] RADEON_CMD_PACKET
error: [drm:pid%d:%s] *ERROR* Packet size provided larger than data provided
error: [drm:pid%d:%s] *ERROR* Invalid colour buffer offset
error: [drm:pid%d:%s] *ERROR* Invalid R200 texture offset
error: [drm:pid%d:%s] *ERROR* Invalid R100 texture offset
error: [drm:pid%d:%s] *ERROR* Invalid R200 cubic texture offset
error: [drm:pid%d:%s] *ERROR* Invalid R100 cubic texture offset
error: [drm:pid%d:%s] *ERROR* Unknown state packet ID %d
error: [drm:pid%d:%s] *ERROR* radeon_emit_packets failed
[drm:pid%d:%s] RADEON_CMD_SCALARS
[drm:pid%d:%s] RADEON_CMD_VECTORS
[drm:pid%d:%s] RADEON_CMD_DMA_DISCARD
error: [drm:pid%d:%s] *ERROR* bad buffer %p %p %d
[drm:pid%d:%s] RADEON_CMD_PACKET3
error: [drm:pid%d:%s] *ERROR* Not a type 3 packet
error: [drm:pid%d:%s] *ERROR* Packet size larger than size of data provided
error: [drm:pid%d:%s] *ERROR* Invalid 3d packet for r100-class chip
error: [drm:pid%d:%s] *ERROR* Too large payload in 3D_LOAD_VBPNTR (count=%d)
error: [drm:pid%d:%s] *ERROR* Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.
error: [drm:pid%d:%s] *ERROR* Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).
error: [drm:pid%d:%s] *ERROR* Invalid 3d packet for r200-class chip
error: [drm:pid%d:%s] *ERROR* Invalid rndr_gen_indx offset
error: [drm:pid%d:%s] *ERROR* Invalid indx_buffer reg address %08X
error: [drm:pid%d:%s] *ERROR* Invalid indx_buffer offset is %08X
error: [drm:pid%d:%s] *ERROR* Invalid first packet offset
error: [drm:pid%d:%s] *ERROR* Invalid second packet offset
error: [drm:pid%d:%s] *ERROR* Invalid packet type %x
[drm:pid%d:%s] RADEON_CMD_PACKET3_CLIP
error: [drm:pid%d:%s] *ERROR* radeon_emit_packet3_clip failed
[drm:pid%d:%s] RADEON_CMD_SCALARS2
[drm:pid%d:%s] RADEON_CMD_WAIT
error: [drm:pid%d:%s] *ERROR* radeon_emit_wait failed
[drm:pid%d:%s] RADEON_CMD_VECLINEAR
error: [drm:pid%d:%s] *ERROR* bad cmd_type %d at %p
error: [drm:pid%d:%s] *ERROR* Packet verification failed
error: [drm:pid%d:%s] *ERROR* radeon_emit_packet3 failed
error: [drm:pid%d:%s] *ERROR* radeon_emit_veclinear failed
RADEON_SE_TCL_MATERIAL_EMMISSIVE_REDR200_SE_TCL_UCP_VERT_BLEND_CTLR200_SE_TCL_OUTPUT_VTX_COMP_SELR200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0[drm:pid%d:%s] 
[drm:pid%d:%s] pid=%d
[drm:pid%d:%s] %d,%d-%d,%d
[drm:pid%d:%s] flags = 0x%x
[drm:pid%d:%s] EAGAIN
[drm:pid%d:%s] dirty=0x%08x
[drm:pid%d:%s] %x
[drm:pid%d:%s] DONE
RADEON_PP_MISCRADEON_PP_CNTLRADEON_RB3D_COLORPITCHRADEON_RE_LINE_PATTERNRADEON_SE_LINE_WIDTHRADEON_PP_LUM_MATRIXRADEON_PP_ROT_MATRIX_0RADEON_RB3D_STENCILREFMASKRADEON_SE_VPORT_XSCALERADEON_SE_CNTLRADEON_SE_CNTL_STATUSRADEON_RE_MISCRADEON_PP_TXFILTER_0RADEON_PP_BORDER_COLOR_0RADEON_PP_TXFILTER_1RADEON_PP_BORDER_COLOR_1RADEON_PP_TXFILTER_2RADEON_PP_BORDER_COLOR_2RADEON_SE_ZBIAS_FACTORRADEON_SE_TCL_OUTPUT_VTX_FMTR200_PP_TXCBLEND_0R200_PP_TXCBLEND_1R200_PP_TXCBLEND_2R200_PP_TXCBLEND_3R200_PP_TXCBLEND_4R200_PP_TXCBLEND_5R200_PP_TXCBLEND_6R200_PP_TXCBLEND_7R200_SE_TCL_LIGHT_MODEL_CTL_0R200_PP_TFACTOR_0R200_SE_VTX_FMT_0R200_SE_VAP_CNTLR200_SE_TCL_MATRIX_SEL_0R200_SE_TCL_TEX_PROC_CTL_2R200_PP_TXFILTER_0R200_PP_TXFILTER_1R200_PP_TXFILTER_2R200_PP_TXFILTER_3R200_PP_TXFILTER_4R200_PP_TXFILTER_5R200_PP_TXOFFSET_0R200_PP_TXOFFSET_1R200_PP_TXOFFSET_2R200_PP_TXOFFSET_3R200_PP_TXOFFSET_4R200_PP_TXOFFSET_5R200_SE_VTE_CNTLR200_PP_TAM_DEBUG3R200_PP_CNTL_XR200_RB3D_DEPTHXY_OFFSETR200_RE_AUX_SCISSOR_CNTLR200_RE_SCISSOR_TL_0R200_RE_SCISSOR_TL_1R200_RE_SCISSOR_TL_2R200_SE_VAP_CNTL_STATUSR200_SE_VTX_STATE_CNTLR200_RE_POINTSIZER200_PP_CUBIC_FACES_0R200_PP_CUBIC_OFFSET_F1_0R200_PP_CUBIC_FACES_1R200_PP_CUBIC_OFFSET_F1_1R200_PP_CUBIC_FACES_2R200_PP_CUBIC_OFFSET_F1_2R200_PP_CUBIC_FACES_3R200_PP_CUBIC_OFFSET_F1_3R200_PP_CUBIC_FACES_4R200_PP_CUBIC_OFFSET_F1_4R200_PP_CUBIC_FACES_5R200_PP_CUBIC_OFFSET_F1_5RADEON_PP_TEX_SIZE_0RADEON_PP_TEX_SIZE_1RADEON_PP_TEX_SIZE_2R200_RB3D_BLENDCOLORR200_SE_TCL_POINT_SPRITE_CNTLRADEON_PP_CUBIC_FACES_0RADEON_PP_CUBIC_OFFSET_T0_0RADEON_PP_CUBIC_FACES_1RADEON_PP_CUBIC_OFFSET_T1_0RADEON_PP_CUBIC_FACES_2RADEON_PP_CUBIC_OFFSET_T2_0R200_PP_TRI_PERFR200_PP_AFS_0R200_PP_AFS_1R200_ATF_TFACTORR200_PP_TXCTLALL_0R200_PP_TXCTLALL_1R200_PP_TXCTLALL_2R200_PP_TXCTLALL_3R200_PP_TXCTLALL_4R200_PP_TXCTLALL_5R200_VAP_PVS_CNTLxiAI
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