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FreeBSD hs32.drive.ne.jp 9.1-RELEASE FreeBSD 9.1-RELEASE #1: Wed Jan 14 12:18:08 JST 2015 root@hs32.drive.ne.jp:/sys/amd64/compile/hs32 amd64
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u%z$FreeBSD: release/9.1.0/sys/dev/drm2/i915/intel_display.c 236931 2012-06-11 21:41:45Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drmP.h 237882 2012-07-01 06:41:39Z mav $$FreeBSD: release/9.1.0/sys/dev/drm2/drm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_atomic.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_internal.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_linux_list.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_mm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_linux_list.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_hashtab.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/i915/i915_drm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/i915/i915_drv.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drm_mm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/i915/i915_reg.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drmP.h 237882 2012-07-01 06:41:39Z mav $$FreeBSD: release/9.1.0/sys/dev/drm2/i915/i915_drm.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/i915/i915_drv.h 235783 2012-05-22 11:07:44Z kib $$FreeBSD: release/9.1.0/sys/dev/drm2/drmP.h 237882 2012-07-01 06:41:39Z mav $GCC: (GNU) 4.2.1 20070831 patched [FreeBSD]onofffalseentruedisPipe [%d]:
  CONF: %08x
  SRC: %08x
  HTOTAL: %08x
  HBLANK: %08x
  HSYNC: %08x
  VTOTAL: %08x
  VBLANK: %08x
  VSYNC: %08x
Plane [%d]:
  CNTR: %08x
  STRIDE: %08x
  SIZE: %08x
  POS: %08x
  ADDR: %08x
  SURF: %08x
  TILEOFF: %08x
Cursor [%d]:
  BASE: %08x
915vbl915cp1915cp2915pip915pr1915pr2915pr3915pr4pm_iir %x
915wfl915flp[drm:KMS:pid%d:%s] 
915trd915trc915frq915dsp915pro915per915fbdBA32sNOTYET: %s at %s:%d
[drm:KMS:pid%d:%s] Sandybridge: intel_iommu_enabled %s -- RC6 %sabled
[drm:KMS:pid%d:%s] RC6 and deep RC6 enabled
[drm:KMS:pid%d:%s] Unknown FSB/MEM found, disable CxSR
[drm:KMS:pid%d:%s] FIFO entries required for mode: %ld
[drm:KMS:pid%d:%s] FIFO watermark level: %ld
PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled
PCH DP (0x%08x) enabled on transcoder %c, should be disabled
plane %c assertion failure, (expected %s, current %s)
pipe %c assertion failure (expected %s, current %s)
panel assertion failure, pipe %c regs locked
FDI RX state assertion failure (expected %s, current %s)
FDI TX state assertion failure (expected %s, current %s)
error: [drm:pid%d:%s] *ERROR* bad pxval: %ld
[drm:KMS:pid%d:%s] watermark %d: display plane %d, fbc lines %d, cursor %d
[drm:KMS:pid%d:%s] fbc watermark(%d) is too large(%d), disabling wm%d+
[drm:KMS:pid%d:%s] display watermark(%d) is too large(%d), disabling wm%d+
[drm:KMS:pid%d:%s] cursor watermark(%d) is too large(%d), disabling wm%d+
[drm:KMS:pid%d:%s] latency %d is 0, disabling wm%d+
[drm:KMS:pid%d:%s] Disabling pch HDMI %x on pipe %d
[drm:KMS:pid%d:%s] Disabling pch dp %x on pipe %d
[drm:KMS:pid%d:%s] vblank wait timed out
[drm:KMS:pid%d:%s] upclocking LVDS
[drm:KMS:pid%d:%s] failed to upclock LVDS!
PLL state assertion failure (expected %s, current %s)
FDI RX PLL assertion failure, should be active but is disabled
FDI TX PLL assertion failure, should be active but is disabled
/usr/src/sys/modules/drm2/i915kms/../../../dev/drm2/i915/intel_display.cerror: [drm:pid%d:%s] *ERROR* mode set failed: pipe %d stuck
[drm:KMS:pid%d:%s] pipe_off wait timed out
plane %c assertion failure, should be disabled but not
plane %c assertion failure, should be off on pipe %c but is still active
error: [drm:pid%d:%s] *ERROR* GT fifo had a previous error %x
info: [drm] Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s
error: [drm:pid%d:%s] *ERROR* timeout waiting for pcode mailbox to become idle
error: [drm:pid%d:%s] *ERROR* timeout waiting for pcode mailbox to finish
[drm:pid%d:%s] overclocking supported, adjusting frequency max to %dMHz
[drm:KMS:pid%d:%s] cancelling pending FBC enable
[drm:KMS:pid%d:%s] more than one pipe active, disabling compression
[drm:KMS:pid%d:%s] no output, disabling
[drm:KMS:pid%d:%s] fbc set to per-chip default
[drm:KMS:pid%d:%s] fbc disabled per module param
[drm:KMS:pid%d:%s] framebuffer too large, disabling compression
[drm:KMS:pid%d:%s] mode incompatible with compression, disabling
[drm:KMS:pid%d:%s] mode too large for compression, disabling
[drm:KMS:pid%d:%s] plane not 0, disabling compression
[drm:KMS:pid%d:%s] framebuffer not tiled or fenced, disabling compression
[drm:KMS:pid%d:%s] disabling active FBC for update
[drm:KMS:pid%d:%s] scheduling delayed FBC enable
[drm:KMS:pid%d:%s] unsupported config, disabling FBC
[drm:KMS:pid%d:%s] disable lvds on pipe %d val 0x%08x
PCH VGA enabled on transcoder %c, should be disabled
PCH LVDS enabled on transcoder %c, should be disabled
error: [drm:pid%d:%s] *ERROR* failed to disable transcoder %d
transcoder assertion failed, should be off on pipe %c but is still active
[drm:KMS:pid%d:%s] has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d
[drm:KMS:pid%d:%s] Using SSC on panel
[drm:KMS:pid%d:%s] Using SSC on eDP
[drm:KMS:pid%d:%s] Disabling SSC entirely
PCH refclk assertion failure, should be active but is disabled
[drm:KMS:pid%d:%s] Wrong PCH DP port return. Guess port B
PCH PLL state assertion failure (expected %s, current %s)
error: [drm:pid%d:%s] *ERROR* failed to enable transcoder %d
[drm:KMS:pid%d:%s] downclocking LVDS
[drm:KMS:pid%d:%s] failed to downclock LVDS!
[drm:pid%d:%s] failed to alloc power context, RC6 disabled
error: [drm:pid%d:%s] *ERROR* failed to pin power context: %d
error: [drm:pid%d:%s] *ERROR* failed to set-domain on power context: %d
error: [drm:pid%d:%s] *ERROR* failed to enable ironlake power power savings
error: [drm:pid%d:%s] *ERROR* pcode write of freq table timed out
[drm:pid%d:%s] gpu busy, RCS change rejected
[drm:pid%d:%s] fmax: %d, fmin: %d, fstart: %d
error: [drm:pid%d:%s] *ERROR* stuck trying to change perf mode
[drm:KMS:pid%d:%s] unsupported pixel format %u
error: [drm:pid%d:%s] *ERROR* framebuffer init failed %d
[drm:KMS:pid%d:%s] Unknown DPLL mode %08x in programmed mode
error: [drm:pid%d:%s] *ERROR* Y tiled not allowed for scan out buffers
error: [drm:pid%d:%s] *ERROR* No FB bound
error: [drm:pid%d:%s] *ERROR* no plane for crtc
error: [drm:pid%d:%s] *ERROR* pin & fence failed
error: [drm:pid%d:%s] *ERROR* failed to update base address
[drm:KMS:pid%d:%s] FBC idle timed out
[drm:KMS:pid%d:%s] disabled FBC
[drm:pid%d:%s] applying pipe a force quirk
error: [drm:pid%d:%s] *ERROR* called with no initialization
error: [drm:pid%d:%s] *ERROR* no such CRTC id
[drm:pid%d:%s] flip queue: crtc already busy
error: [drm:pid%d:%s] *ERROR* Prepared flip multiple times
[drm:pid%d:%s] preparing flip with no unpin work?
[drm:KMS:pid%d:%s] [CONNECTOR:%d:%s], [ENCODER:%d:%s]
[drm:KMS:pid%d:%s] no pipe available for load-detect
[drm:KMS:pid%d:%s] creating tmp fb for load-detection
[drm:KMS:pid%d:%s] reusing fbdev for load-detection framebuffer
[drm:KMS:pid%d:%s] failed to allocate framebuffer for load-detection
[drm:KMS:pid%d:%s] failed to set mode on load-detect pipe
[drm:KMS:pid%d:%s] cursor off
error: [drm:pid%d:%s] *ERROR* we currently only support 64x64 cursors
error: [drm:pid%d:%s] *ERROR* buffer is to small
error: [drm:pid%d:%s] *ERROR* cursor cannot be tiled
error: [drm:pid%d:%s] *ERROR* failed to move cursor bo into the GTT
error: [drm:pid%d:%s] *ERROR* failed to release fence for cursor
error: [drm:pid%d:%s] *ERROR* failed to attach phys object
[drm:KMS:pid%d:%s] ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]
[drm:KMS:pid%d:%s] ELD on pipe %c
[drm:KMS:pid%d:%s] Audio directed to unknown port
[drm:KMS:pid%d:%s] ELD on port %c
[drm:KMS:pid%d:%s] ELD: DisplayPort detected
[drm:KMS:pid%d:%s] ELD size %d
[drm:KMS:pid%d:%s] failed to compute sprite wm for pipe %d
[drm:KMS:pid%d:%s] sprite watermarks For pipe %d - %d
[drm:KMS:pid%d:%s] failed to compute sprite lp1 wm on pipe %d
[drm:KMS:pid%d:%s] failed to compute sprite lp2 wm on pipe %d
[drm:KMS:pid%d:%s] failed to compute sprite lp3 wm on pipe %d
[drm:KMS:pid%d:%s] FIFO watermarks For pipe A - plane %d, cursor: %d
[drm:KMS:pid%d:%s] FIFO watermarks For pipe B - plane %d, cursor: %d
[drm:KMS:pid%d:%s] FIFO watermarks For pipe C - plane %d, cursor: %d
[drm:KMS:pid%d:%s] Setting FIFO watermarks - A: %d
[drm:KMS:pid%d:%s] self-refresh entries: %d, wm: %d
[drm:KMS:pid%d:%s] self-refresh watermark: display plane %d cursor %d
[drm:KMS:pid%d:%s] Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d
[drm:KMS:pid%d:%s] SR watermark: display plane %d, cursor %d
[drm:KMS:pid%d:%s] display watermark is too large(%d/%ld), disabling
[drm:KMS:pid%d:%s] cursor watermark is too large(%d/%ld), disabling
[drm:KMS:pid%d:%s] SR latency is 0, disabling
[drm:KMS:pid%d:%s] Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d
[drm:KMS:pid%d:%s] DSPFW1 register is %x
[drm:KMS:pid%d:%s] DSPFW3 register is %x
[drm:KMS:pid%d:%s] Self-refresh is enabled
[drm:KMS:pid%d:%s] Self-refresh is disabled
[drm:KMS:pid%d:%s] FIFO size - (0x%08x) %s: %d
error: [drm:pid%d:%s] *ERROR* Can't update pipe %c in SAREA
[drm:KMS:pid%d:%s] crtc %d/%d dpms on
[drm:KMS:pid%d:%s] crtc %d/%d dpms off
[drm:KMS:pid%d:%s] FDI_RX_IIR 0x%x
[drm:KMS:pid%d:%s] FDI train 1 done.
error: [drm:pid%d:%s] *ERROR* FDI train 1 fail!
[drm:KMS:pid%d:%s] FDI train 2 done.
error: [drm:pid%d:%s] *ERROR* FDI train 2 fail!
[drm:KMS:pid%d:%s] FDI train done.
[drm:KMS:pid%d:%s] FDI train done
error: [drm:pid%d:%s] *ERROR* Can't update plane %d in SAREA
error: [drm:pid%d:%s] *ERROR* bpp 16, depth %d
error: [drm:pid%d:%s] *ERROR* bpp %d depth %d
error: [drm:pid%d:%s] *ERROR* Unknown color depth %d
[drm:KMS:pid%d:%s] Writing base %08lX %08lX %d %d %d
[drm:KMS:pid%d:%s] enabled fbc on plane %d
[drm:KMS:pid%d:%s] enabled FBC, pitch %d, yoff %d, plane %d, [drm:KMS:pid%d:%s] using SSC reference clock of %d MHz
error: [drm:pid%d:%s] *ERROR* Couldn't find PLL settings for mode!
[drm:KMS:pid%d:%s] Mode for pipe %c:
info: [drm] Changing LVDS panel from (%chsync, %cvsync) to (%chsync, %cvsync)
[drm:KMS:pid%d:%s] enabling CxSR downclocking
[drm:KMS:pid%d:%s] disabling CxSR downclocking
[drm:KMS:pid%d:%s] FIFO watermarks - A: %d, B: %d
[drm:KMS:pid%d:%s] self-refresh entries: %d
[drm:KMS:pid%d:%s] Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d
[drm:KMS:pid%d:%s] memory self refresh enabled
[drm:KMS:pid%d:%s] memory self refresh disabled
[drm:KMS:pid%d:%s] clamping display bpc (was %d) to LVDS (%d)
[drm:KMS:pid%d:%s] clamping display bpc (was %d) to eDP (%d)
[drm:KMS:pid%d:%s] clamping display bpc (was %d) to EDID reported max of %d
[drm:KMS:pid%d:%s] forcing bpc to 12 for HDMI
[drm:KMS:pid%d:%s] forcing bpc to 8 for HDMI
[drm:KMS:pid%d:%s] Dithering DP to 6bpc
[drm:pid%d:%s] unsupported depth, assuming 24 bits
[drm:KMS:pid%d:%s] setting pipe bpc to %d (max display bpc %d)
intel_choose_pipe_bpp returned invalid value %d
[drm:KMS:pid%d:%s] Mode for pipe %d:
[drm:KMS:pid%d:%s] using pipe a dpll
[drm:KMS:pid%d:%s] using pipe b dpll
[drm:KMS:pid%d:%s] no matching PLL configuration for pipe 2
[drm:KMS:pid%d:%s] eDP PLL enable for clock %d
[drm:KMS:pid%d:%s] Using MT version of forcewake
[drm:KMS:pid%d:%s] Failed to get proper latency. Disable CxSR
[drm:KMS:pid%d:%s] Failed to read display plane latency. Disable CxSR
info: [drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR
[drm:KMS:pid%d:%s] %d display pipe%s available.
[drm:KMS:pid%d:%s] swapping pipes & planes for FBC
[drm:KMS:pid%d:%s] plane %d init failed: %d
[drm:KMS:pid%d:%s] HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d
[drm:KMS:pid%d:%s] probing SDVOB
[drm:KMS:pid%d:%s] probing HDMI on SDVOB
[drm:KMS:pid%d:%s] probing DP_B
[drm:KMS:pid%d:%s] probing SDVOC
[drm:KMS:pid%d:%s] probing HDMI on SDVOC
[drm:KMS:pid%d:%s] probing DP_C
[drm:KMS:pid%d:%s] probing DP_D
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