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/***********************license start***************
 * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
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 ***********************license end**************************************/

/**
 * @file
 *
 * Interface to power-throttle control, measurement, and debugging
 * facilities.
 *
 * <hr>$Revision<hr>
 *
 */

#include "cvmx.h"
#include "cvmx-asm.h"
#include "cvmx-power-throttle.h"

#define CVMX_PTH_PPID_BCAST	63
#define CVMX_PTH_PPID_MAX	64

/**
 * @INTERNAL
 * Set the POWLIM field as percentage% of the MAXPOW field in r.
 */
static uint64_t __cvmx_power_throttle_set_powlim(uint64_t r, uint8_t percentage)
{
    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
    {
        uint64_t t;

        assert(percentage < 101);
        t = percentage * cvmx_power_throttle_get_field(CVMX_PTH_INDEX_MAXPOW, r) / 100;
        r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t);

        return r;
    }
    return 0;
}

/**
 * @INTERNAL
 * Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR
 * address. (ppid == PTH_PPID_BCAST is for broadcasting)
 */
static uint64_t __cvmx_power_throttle_csr_addr(uint64_t ppid)
{
    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
    {
        uint64_t csr_addr, reg_num, reg_reg, reg_sel;

        assert(ppid < CVMX_PTH_PPID_MAX);
        /*
         * register 11 selection 6
         */
        reg_reg = 11;
        reg_sel = 6;
        reg_num = (ppid << 8) + (reg_reg << 3) + reg_sel;
        csr_addr = CVMX_L2C_COP0_MAPX(0) + ((reg_num) << 3);

        return csr_addr;
    }
    return 0;
}

/**
 * Throttle power to percentage% of configured maximum (MAXPOW).
 *
 * @param percentage	0 to 100
 * @return 0 for success
 */
int cvmx_power_throttle_self(uint8_t percentage)
{
    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
    {
        uint64_t r; 

        CVMX_MF_COP0(r, COP0_POWTHROTTLE);
        r = __cvmx_power_throttle_set_powlim(r, percentage);
        CVMX_MT_COP0(r, COP0_POWTHROTTLE);
    }

    return 0;
}

/**
 * Throttle power to percentage% of configured maximum (MAXPOW)
 * for the cores identified in coremask.
 *
 * @param percentage 	0 to 100
 * @param coremask	bit mask where each bit identifies a core.
 * @return 0 for success.
 */
int cvmx_power_throttle(uint8_t percentage, uint64_t coremask)
{
    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
    {
        uint64_t ppid, csr_addr, b, r;

        b = 1;
        /*
         * cvmx_read_csr() for PTH_PPID_BCAST does not make sense and
         * therefore limit ppid to less.
         */
        for (ppid = 0; ppid < CVMX_PTH_PPID_BCAST; ppid ++)
        {
            if ((b << ppid) & coremask) {
                csr_addr = __cvmx_power_throttle_csr_addr(ppid);
                r = cvmx_read_csr(csr_addr);
                r = __cvmx_power_throttle_set_powlim(r, percentage);
                cvmx_write_csr(csr_addr, r);
            }
        }
    }

    return 0;
}