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	tp_pmtx = 50

	# TP TX payload page size
	tp_pmtx_pagesize = 64K

# Some "definitions" to make the rest of this a bit more readable.  We support
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
# per function per port ...
#
# NMSIX = 1088			# available MSI-X Vectors
# NVI = 128			# available Virtual Interfaces
# NMPSTCAM = 336		# MPS TCAM entries
#
# NPORTS = 4			# ports
# NCPUS = 8			# CPUs we want to support scalably
# NFUNCS = 3			# functions per port (NIC, FCoE, iSCSI)

# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
# PF" which many OS Drivers will use to manage most or all functions.
#
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
# use Forwarded Interrupt Ingress Queues.  For these latter, an Ingress Queue
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
# will be specified as the "I!"!"(-$üÿÿÿÿÿÿÿ> M#T#[	`$üÿÿÿÿÿÿÿns)üÿÿÿÿÿÿÿ‘	–)üÿÿÿÿÿÿÿ¤©)üÿÿÿÿÿÿÿ[0[p[[P[[¨[ [8[´[@[!X['`[À[x[À[€[!˜[Ø[ [-À[!È[
	



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 x_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 1			# 1 port
	niqflint = 8		# NCPUS "Queue Sets"
	nethctrl = 8		# NCPUS "Queue Sets"
	neq = 16		# niqflint + nethctrl Egress Queues
	nexactf = 8		# number of exact MPSTCAM MAC filters
	cmask = all		# access to all channels
	pmask = 0x1		# access to only one port

[function "1"]
	nvf = 16		# NVF on this function
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 1			# 1 port
	niqflint = 8		# NCPUS "Queue Sets"
	nethctrl = 8		# NCPUS "Queue Sets"
	neq = 16		# niqflint + nethctrl Egress Queues
	nexactf = 8		# number of exact MPSTCAM MAC filters
	cmask = all		# access to all channels
	pmask = 0x2		# access to only one port

[function "2"]
	nvf = 16		# NVF on this function
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 1			# 1 port
	niqflint = 8		# NCPUS "Queue Sets"
	nethctrl = 8		# NCPUS "Queue Sets"
	neq = 16		# niqflint + nethctrl Egress Queues
	nexactf = 8		# number of exact MPSTCAM MAC filters
	cmask = all		# access to all channels
	pmask = 0x4		# access to only one port

[function "3"]
	nvf = 16		# NVF on this function
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 1			# 1 port
	niqflint = 8		# NCPUS "Queue Sets"
	nethctrl = 8		# NCPUS "Queue Sets"
	neq = 16		# niqflint + nethctrl Egress Queues
	nexactf = 8		# number of exact MPSTCAM MAC filters
	cmask = all		# access to all channels
	pmask = 0x8		# access to only one port

# Some OS Drivers manage all application functions for all ports via PF4.
# Thus we need to provide a large number of resources here.  For Egress
# Queues we need to account for both TX Queues as well as Free List Queues
# (because the host is responsible for producing Free List Buffers for the
# hardware to consume).
#
[function "4"]
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 28		# NVI_UNIFIED
	niqflint = 170		# NFLIQ_UNIFIED + NLFIQ_WD
	nethctrl = 100		# NETHCTRL_UNIFIED + NETHCTRL_WD
	neq = 256		# NEQ_UNIFIED + NEQ_WD
	nexactf = 40		# NMPSTCAM_UNIFIED
	cmask = all		# access to all channels
	pmask = all		# access to all four ports ...
	nethofld = 1024		# number of user mode ethernet flow contexts
	nroute = 32		# number of routing region entries
	nclip = 32		# number of clip region entries
	nfilter = 496		# number of filter region entries
	nserver = 496		# number of server region entries
	nhash = 12288		# number of hash region entries
	protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu
	tp_l2t = 3072
	tp_ddp = 2
	tp_ddp_iscsi = 2
	tp_stag = 2
	tp_pbl = 5
	tp_rq = 7

# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
# "Queue Sets" each.
#
[function "5"]
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 4			# NPORTS
	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
	nethctrl = 32		# NPORTS*NCPUS
	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
	nexactf = 4		# NPORTS
	cmask = all		# access to all channels
	pmask = all		# access to all four ports ...
	nserver = 16
	nhash = 2048
	tp_l2t = 1024
	protocol = iscsi_initiator_fofld
	tp_ddp_iscsi = 2
	iscsi_ntask = 2048
	iscsi_nsess = 2048
	iscsi_nconn_per_session = 1
	iscsi_ninitiator_instance = 64

[function "6"]
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 4			# NPORTS
	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
	nethctrl = 32		# NPORTS*NCPUS
	neq = 66		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
	nexactf = 32		# NPORTS + adding 28 exact entries for FCoE
				# which is OK since < MIN(SUM PF0..3, PF4)
				# and we never load PF0..3 and PF4 concurrently
	cmask = all		# access to all channels
	pmask = all		# access to all four ports ...
	nhash = 2048
	protocol = fcoe_initiator
	tp_ddp = 2
	fcoe_nfcf = 16
	fcoe_nvnp = 32
	fcoe_nssn = 1024

# The following function, 1023, is not an actual PCIE function but is used to
# configure and reserve firmware internal resources that come from the global
# resource pool.
#
[function "1023"]
	wx_caps = all		# write/execute permissions for all commands
	r_caps = all		# read permissions for all commands
	nvi = 4			# NVI_UNIFIED
	cmask = all		# access to all channels
	pmask = all		# access to all four ports ...
	nexactf = 8		# NPORTS + DCBX +
	nfilter = 16		# number of filter region entries

# For Virtual functions, we only allow NIC functionality and we only allow
# access to one port (1 << PF).  Note that because of limitations in the
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
# and GTS registers, the number of Ingress and Egress Queues must be a power
# of 2.
#
[function "0/*"]		# NVF
	wx_caps = 0x82		# DMAQ | VF
	r_caps = 0x86		# DMAQ | VF | PORT
	nvi = 1			# 1 port
	niqflint = 4		# 2 "Queue Sets" + NXIQ
	nethctrl = 2		# 2 "Queue Sets"
	neq = 4			# 2 "Queue Sets" * 2
	nexactf = 4
	cmask = all		# access to all channels
	pmask = 0x1		# access to only one port ...

[function "1/*"]		# NVF
	wx_caps = 0x82		# DMAQ | VF
	r_caps = 0x86		# DMAQ | VF | PORT
	nvi = 1			# 1 port
	niqflint = 4		# 2 "Queue Sets" + NXIQ
	nethctrl = 2		# 2 "Queue Sets"
	neq = 4			# 2 "Queue Sets" * 2
	nexactf = 4
	cmask = all		# access to all channels
	pmask = 0x2		# access to only one port ...

[function "2/*"]		# NVF
	wx_caps = 0x82		# DMAQ | VF
	r_caps = 0x86		# DMAQ | VF | PORT
	nvi = 1			# 1 port
	niqflint = 4		# 2 "Queue Sets" + NXIQ
	nethctrl = 2		# 2 "Queue Sets"
	neq = 4			# 2 "Queue Sets" * 2
	nexactf = 4
	cmask = all		# access to all channels
	pmask = 0x4		# access to only one port ...

[function "3/*"]		# NVF
	wx_caps = 0x82		# DMAQ | VF
	r_caps = 0x86		# DMAQ | VF | PORT
	nvi = 1			# 1 port
	niqflint = 4		# 2 "Queue Sets" + NXIQ
	nethctrl = 2		# 2 "Queue Sets"
	neq = 4			# 2 "Queue Sets" * 2
	nexactf = 4
	cmask = all		# access to all channels
	pmask = 0x8		# access to only one port ...

# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
# folling params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem:	%-age of mem to use for port/buffer group
# lpbk_mem:	%-age of port/bg mem to use for loopback
# hwm:		high watermark; bytes available when starting to send pause
#		frames (in units of 0.1 MTU)
# lwm:		low watermark; bytes remaining when sending 'unpause' frame
#		(in inuits of 0.1 MTU)
# dwm:		minimum delta between high and low watermark (in units of 100
#		Bytes)
#
[port "0"]
	dcb = ppp, dcbx		# configure for DCB PPP and enable DCBX offload
	bg_mem = 25
	lpbk_mem = 25
	hwm = 30
	lwm = 15
	dwm = 30

[port "1"]
	dcb = ppp, dcbx
	bg_mem = 25
	lpbk_mem = 25
	hwm = 30
	lwm = 15
	dwm = 30

[port "2"]
	dcb = ppp, dcbx
	bg_mem = 25
	lpbk_mem = 25
	hwm = 30
	lwm = 15
	dwm = 30

[port "3"]
	dcb = ppp, dcbx
	bg_mem = 25
	lpbk_mem = 25
	hwm = 30
	lwm = 15
	dwm = 30

[fini]
	version = 0x1425000b
	checksum = 0x7690f7a5

# Total resources used by above allocations:
#   Virtual Interfaces: 104
#   Ingress Queues/w Free Lists and Interrupts: 526
#   Egress Queues: 702
#   MPS TCAM Entries: 336
#   MSI-X Vectors: 736
#   Virtual Functions: 64
#
# $FreeBSD: release/9.1.0/sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt 237925 2012-07-01 13:43:30Z np $
#
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