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	DHsI$HSHLNLFLVL)MDHQL)MDHsI$0RHLNLFLVL)MDDHQL)MDHsI$SHLNLFLVL)MDHQL)MDHsI$SHLNLFLVL)MRDHQL)M)DHsI$RHLNLFLVL)MDHQL)MDHsH{XI$p1[A\fDDHQL)MJL4LLNLVLFLfLLNLVLFfDJJJLNLVLFDJJLNLVLFDJ\JLNLVLF'DJJLNLVLFdDJ JLNLVLFDJJLNLVLFrDJ.JLNLVLFDJ!JLNLVLFDJJLNLVLFsDJ/JLNLVLFDJJLNLVLFDJ=JLNLVLFDJJLNLVLFDJKJLNLVLFDJJLNLVLFDJ1JLNLVLFDJJLNLVLFDJ?JLNLVLF
DJJLNLVLFDJMJLNLVLFDJJLNLVLFDJ[JLNLVLF&DJJLNLVLFDJiJLNLVLF4DJJLNLVLFDJwJLNLVLFBDJJLNLVLFDJJLNLVLFPDJJLNLVLFDJJLNLVLF^DJJLNLVLFDJJLNLVLFnDJJJLNLVLFDJJLNLVLFDJXJLNLVLF#DJJLNLVLFDJfJLNLVLF1DJJLNLVLFDJtJLNLVLF?DJJLNLVLFDJJLNLVLFMDJ	JLNLVLFDJJLNLVLF[DJJLNLVLFDJJLNLVLFiDJ(JLNLVLFDJJLNLVLF}DJ9JLNLVLFDJJLNLVLFDJGJLNLVLFDJJLNLVLFDJUJLNLVLF DJJLNLVLFDJcJLNLVLF.DJJLNLVLFDJqJLNLVLF<DJJLNLVLFDJJLNLVLFJDJJLNLVLFDJJLNLVLFXDJJLNLVLFDJJLNLVLFfDJ"JLNLVLFDJJLNLVLFtDJ0JLNLVLFDJJLNLVLFDJ>JLNLVLF	DJJLNLVLFDJLJLNLVLFDJJLNLVLFDJZJLNLVLF%DJJLNLVLFDJhJLNLVLF3DJJLNLVLFDJvJLNLVLFADJJLNLVLFDJJLNLVLFODJJLNLVLFDJJLNLVLF]DUHAUATSHHm0HwLLNI$(pLFLVHL)MJ0JHQLNLFLVL)M=0DHsI$@pHLNLFLVL)MBDHQL)MBDHsI$XpHLNLFLVL)M#6DHQL)M5DHsI$ppHLNLFLVL)M5DHQL)M5DHsI$pHLNLFLVL)My;DHQL)MQ;DHsI$pHLNLFLVL)M;DHQL)M:DHsI$pHLNLFLVL)M:DHQL)Mk:DHsI$pHLNLFLVL)M :DHQL)M9DHsI$4HLNLFLVL)M;DHQL)M};DHsI$@4HLNLFLVL)M2;DHQL)M
;DHsI$4HLNLFLVL)M:DHQL)M:DHsI$'HLNLFLVL)ML:DHQL)M$:DHsI$('HLNLFLVL)M9DHQL)M9DHsI$@'HLNLFLVL)Mf9DHQL)M>9DHsI$X'HLNLFLVL)M8DHQL)M8DHsI$'HLNLFLVL)M8DHQL)MX8DHsI$
HLNLFLVL)Mg>DHQL)M?>DHsI$(
HLNLFLVL)M=DHQL)M=DHsI$@
HLNLFLVL)M=DHQL)MY=DHsI$X
HLNLFLVL)M=DHQL)M<DHsI$p
HLNLFLVL)M<DHQL)Ms<DHsI$
HLNLFLVL)M(<DHQL)M<DHsI$
HLNLFLVL)M;DHQL)M;DHsI$
HLNLFLVL)MB;DHQL)M;DHsI$
HLNLFLVL)M:DHQL)M:DHsI$HLNLFLVL)M\:DHQL)M4:DHsI$HLNLFLVL)M9DHQL)M9DHsI$0HLNLFLVL)Mv9DHQL)MN9DHsI$HHLNLFLVL)M9DHQL)M8DHsI$
HLNLFLVL)M8DHQL)Mh8DHsI$)HLNLFLVL)M8DHQL)M7DHsI$)HLNLFLVL)M7DHQL)M7DHsI$6HLNLFLVL)MA-DHQL)M-D1ɿHsM(6LLNLFLVL)M}'BICL)MX'BHsMp6LLNLFLVL)M'BICL)M&BHHhHsI$6HLNLFLVL)M/,DHQL)M,DHsI$KHLNLFLVL)M-DHQL)M,DHsI$@KHLNLFLVL)M,DHQL)Mq,DHsI$(KHLNLFLVL)M&,DHQL)M+DHsI$KHLNLFLVL)M+DHQL)M+DHsI$HLNLFLVL)M8-DHQL)M-DHsI$HLNLFLVL)M,DHQL)M,DHsI$HLNLFLVL)MR,DHQL)M*,DHsI$HLNLFLVL)M+DHQL)M+DHsI$:HLNLFLVL)Ml+DHQL)MD+DHsI$:HLNLFLVL)M*DHQL)M*DHsI$OHLNLFLVL)M*DHQL)M^*DHsI$POHLNLFLVL)M*DHQL)M)DHsI$(OHLNLFLVL)M-DHQL)Mh-DHsI$OHLNLFLVL)M-DHQL)M,DHsI$HLNLFLVL)M,DHQL)M,DHsI$HLNLFLVL)M7,DHQL)M,DHsI$HLNLFLVL)M+DHQL)M+DHsI$XHLNLFLVL)MQ+DHQL)M)+DHsI$pHLNLFLVL)M*DHQL)M*DHsI$HLNLFLVL)Mk*DHQL)MC*DHsI$0HLNLFLVL)M)DHQL)M)DHsI$HHLNLFLVL)M)DHQL)M])DHsI$HLNLFLVL)M)DHQL)M(DHsI$YHLNLFLVL)M(DHQL)Mw(DHsI$(YHLNLFLVL)M,(DHQL)M(DHsI$YHLNLFLVL)M'DHQL)M'DHsI$HLNLFLVL)MF'DHQL)M'DHsI$HLNLFLVL)M&DHQL)M&DHsI$0HLNLFLVL)M#DHQL)M#DHsI$(0HLNLFLVL)MM#DHQL)M%#DHsI$VHLNLFLVL)M"DHQL)M"DHsI$0HLNLFLVL)Mg"DHQL)M?"DHsIL$HLNLFLVL)M!DHQL)M!DHsLLNLFLVL)M!DIT$L)Mc!DHsI$XHLNLFLVL)M!DHQL)M DHsI$(XHLNLFLVL)M DHQL)M} DHsI$@XHLNLFLVL)M2 DHQL)M
 DHsI$XHLNLFLVL)MDHQL)MDHsI$HLNLFLVL)MLDHQL)M$DHsI$HLNLFLVL)MDHQL)MDHsI$RHLNLFLVL)MfDHQL)M>DHsI$@SHLNLFLVL)MDHQL)MDHsI$(RHLNLFLVL)MDHQL)MXDHsI$SHLNLFLVL)M
DHQL)MDHsI$SHLNLFLVL)MDHQL)MrDHsI$RHLNLFLVL)M'DHQL)MDHsI$pI$pHNLNLFH)MBHH)MBI$0pLNLFLVHL)M_DHQL)M7DHsI$HpHLNLFLVL)MDHQL)M3DHsI$`pHLNLFLVL)MyDHQL)MQDHsI$xpHLNLFLVL)MDHQL)MDHsI$pHLNLFLVL)MDHQL)MkDHsI$pHLNLFLVL)M DHQL)MDHsI$pHLNLFLVL)MDHQL)MDHsI$pHLNLFLVL)M:DHQL)MDHsI$4HLNLFLVL)MDHQL)MDHsI$H4HLNLFLVL)MTDHQL)M,DHsI$4HLNLFLVL)MDHQL)MDHsI$'HLNLFLVL)MnDHQL)MFD11HHHH	ƒuHsIM$0'ILLLVLFH L^L)MBDIEL)MB11HHHH	ƒuHsIM$H'ILLLVLFH L^L)M$BDIEL)M$BHsI$`'HLNLFLVL)M@$DHQL)M$DHsI$'HLNLFLVL)M#DHQL)M#DHsI$
HLNLFLVL)MZ#DHQL)M2#WD11HHHH	ƒuHsIM$0
ILLLVLFH L^L)M"BDIEL)M"B11HHHH	ƒuHsIM$H
ILLLVLFH L^L)M,"BDIEL)M
"B11HHHH	ƒuHsIM$`
ILLLVLFH L^L)M!BDIEL)Mp!BHsI$x
HLNLFLVL)M'!DHQL)M `D11HDHHH	ƒuHsIM$
ILLLVLFH L^L)M BDIEL)Me BHsI$
HLNLFLVL)M DHQL)MD11HDHHH	ƒuHsIM$
ILLLVLFH L^L)M|BDIEL)MZBHsI$
HLNLFLVL)MDHQL)MKDHsI$HLNLFLVL)MDHQL)MvDHsI$ HLNLFLVL)M+DHQL)MDHsI$8HLNLFLVL)MDHQL)MDHsI$PHLNLFLVL)MEDHQL)MDHsI$
HLNLFLVL)MDHQL)M?p
DHsI$)HLNLFLVL)MgDHQL)M?DHsI$)HLNLFLVL)MDHQL)MDHsI$6HLNLFLVL)MDHQL)MYD1ɿHsM@6LLNLFLVL)MVDICL)M/BHsM̈6LLNLFLVL)M
BISL)M
DHHdHsI$6HLNLFLVL)M'DHQL)M'DHsI$KHLNLFLVL)M'DHQL)MZ'DHsI$HKHLNLFLVL)M'DHQL)M&DHsI$0KHLNLFLVL)M&DHQL)Mt&DHsI$KHLNLFLVL)M)&DHQL)M&DHsI$HLNLFLVL)M%DHQL)M%DHsI$HLNLFLVL)MC%DHQL)M%DHsI$HLNLFLVL)M$DHQL)M$DHsI$HLNLFLVL)M]$DHQL)M5$DHsI$:HLNLFLVL)M#DHQL)M#?DHsI$:HLNLFLVL)Mw#DHQL)MO#DHsI$OHLNLFLVL)M#?DHQL)M"1DHsI$XOHLNLFLVL)M"DHQL)Ml"DHsI$0OHLNLFLVL)M!"0?DHQL)M!DHsI$OHLNLFLVL)M!DHQL)M!DHsI$HLNLFLVL)M;!DHQL)M!DHsI$HLNLFLVL)M DHQL)M DHsI$HLNLFLVL)MU DHQL)M- DHsI$`HLNLFLVL)MDHQL)MDHsI$xHLNLFLVL)MoDHQL)MGDHsI$HLNLFLVL)MDHQL)MDHsI$8HLNLFLVL)MDHQL)MaDHsI$PHLNLFLVL)MDHQL)MDHsI$HLNLFLVL)MDHQL)M{DHsI$YHLNLFLVL)M0DHQL)MDHsI$0YHLNLFLVL)MDHQL)MDHsI$YHLNLFLVL)MJDHQL)M"DHsI$HLNLFLVL)MDHQL)MDHsI$HLNLFLVL)MdDHQL)M<DHsI$0HLNLFLVL)MDHQL)MDHsI$00HLNLFLVL)M~DHQL)MVDHsI$ VHLNLFLVL)MDHQL)M3˲DHsI$0HLNLFLVL)MDHQL)MpDHsIL$HLNLFLVL)M(DHQL)MDHsIL$HLNLFLVL)MDHQL)MDHsI$XHLNLFLVL)MEDHQL)MDHsI$0XHLNLFLVL)MDHQL)MDHsI$HXHLNLFLVL)M_DHQL)M7DHsI$XHLNLFLVL)MDHQL)MDHsI$HLNLFLVL)MyDHQL)MQDHsI$HLNLFLVL)MDHQL)MDHsI$RHLNLFLVL)MDHQL)MkDHsI$HSHLNLFLVL)M DHQL)MDHsI$0RHLNLFLVL)MDHQL)MDHsI$SHLNLFLVL)M:DHQL)M1DHsI$SHLNLFLVL)M??DHQL)MDHsI$RHLNLFLVL)MWDHQL)M/DHsH{XI$p1H[A\A]øDHQL)MJJ9LLNLVLFLJLNLVLFLLLNLVLFLLLNLVLFpL؉LLDLVL^LFJJLNLVLFJAJLNLVLF
JJLNLVLFJ[JLNLVLF'JJLNLVLFJuJLNLVLFAJJLNLVLFJJLNLVLF[JJLNLVLFJJLNLVLFuJ36JLNLVLFJJLNLVLFLYL;JJLNLVLFJJLNLVLFTJJLNLVLFJJLNLVLFnJ/JLNLVLFJJLNLVLFJIJLNLVLFJJLNLVLFJcJLNLVLF/JJLNLVLFJ}JLNLVLFIJ
JLNLVLFJJLNLVLFbJ+JLNLVLFJJLNLVLFJHJLNLVLFJJLNLVLFJbJLNLVLF.JJLNLVLFJJLNLVLFJrJLNLVLF>JJLNLVLFJoJLNLVLF;JJLNLVLFJJLNLVLFUJJLNLVLFJJLNLVLFJJLNLVLFhJ)JLNLVLFJJLNLVLFJCJLNLVLFJJLNLVLFJ]JLNLVLF)JJLNLVLFJOJLNLVLFJJLNLVLFJiJLNLVLF5JJLNLVLFJJLNLVLFOJJLNLVLFJJLNLVLFiJ*JLNLVLFJJLNLVLFJDJLNLVLFJJLNLVLFJ^JLNLVLF*JJLNLVLFJxJLNLVLFDJJLNLVLFJJLNLVLF^JJLNLVLFmJ.JLNLVLFJJLNLVLFJ?p
HJLNLVLFJJLNLVLFJJLNLVLF[JJLNLVLFJJLNLVLFuJJLNLVLFnJ/JLNLVLFJJLNLVLFJIJLNLVLFJJLNLVLFJcJLNLVLF/JJLNLVLFJ}JLNLVLFIJJLNLVLFJjJLNLVLF6JJLNLVLFJJLNLVLFPJKJLNLVLFL؉LDLVL^LFuJJLNLVLFL؉LDLVL^LFjJ`JLNLVLFL؉LDLVL^LF_L؉LDLVL^LFL؉`LDLVL^LF2JWJLNLVLFJUJLNLVLF!JJLNLVLFL؉tLDLVL^LFFJxJLNLVLFDJJLNLVLFJJLNLVLF^JJLNLVLFJJLNLVLFxJ9JLNLVLFJJLNLVLFJSJLNLVLFJJLNLVLFJmJLNLVLF9JJLNLVLFJJLNLVLFSJJLNLVLFJJLNLVLFmJ.JLNLVLFJJLNLVLFJJJLNLVLFJJLNLVLFJXJ??LNLVLF$JJLNLVLFJuJLNLVLFAJJLNLVLFJJLNLVLF[JJLNLVLFJJLNLVLFuJ6JLNLVLFJJLNLVLFJPJLNLVLFJJLNLVLFJjJLNLVLF6JJLNLVLFJJLNLVLFVJ3˲JLNLVLFJJLNLVLFpJ1JLNLVLFJJLNLVLFJKJLNLVLFJJLNLVLFJeJLNLVLF1JJLNLVLFJJLNLVLFKJJLNLVLFJJLNLVLFeJ&JLNLVLFJJLNLVLFJ@JLNLVLFJJLNLVLFJZJLNLVLF&JJLNLVLFJtJLNLVLF@JJ0?LNLVLFJJLNLVLFZJJ?LNLVLFJJLNLVLFwJ?8JLNLVLFJJLNLVLFJRJLNLVLFJJLNLVLFJlJLNLVLF8JJLNLVLFJJLNLVLFRJJLNLVLFJJLNLVLFlJ-JLNLVLFUHH H$Ll$HLt$Ld$AMoH5LHAH8H	HHKH0H	ANpH LHqH	ALIHH	ljHH	LIH)I HyB1I@H)HBDJpHHsH{XD1IuAEv-At'AtfA1H$Ld$Ll$Lt$ÐHCJpHHxHpHQH)Hxt_H2H)H1HfA1LDELȉ8HqLIHQH5PuH5PxH)1H5P]fDUHH0H]LeHLmLuAuH]LeLmLuLu޲AfEMuDzMADHuMApDHu}EKDHH5ǀEި@tKDHH5fEިKDHH5ǀEިtKDHH5fEިxKDHH5ǀEtKDHH5fMAtDH}yKDHH5fEި@tKDHH5fEިtKDHH5fEިtKDHH5fEިtKDHH5fEިKDHH5f
EDHKDHHH5fHH5H5KDDHHHH5fHH5H5TKDDHHHH5fHH5H5fDfDUHAWAVIAUATSHH(DEH}HMLSLKHp8H<LCL)M{BHL)M[BHʉH H	M,IETIMPL)M(BHL)MBHH H	I<HHL)MBAHL)MBLHH H	HL)MxBHL)MXBH1HH HH8HAHHHHuE1IIL)MQL0HL)MSBHH H	IH$|L |L)MBLL)MBHHH H	‰H	LHL)ЉH M=BICL)MBH{HL)M1DHQL)MD¢H(D[A\A]A^A_LL8LNLD/LL0LLBHL)MLIpHUHHHL)MBHL)McBHH H	IHH@HDL)M0BHL)MBHAHUHKLKLCIՐHFH)ML8HH)MBHDMH LEH}H	DHIAqLSLCLKXJGJLSLCLKL8LSLCLKLLSLCLKL0rL8RLL0LL0zBHH)MLUHSHHH5HtHHǃ5H1[UHHLd$H$IuH$Ld$HHHt&HǾI$5H1뮸IDŽ$5fUHATSHt7t8E1DJHsH{XIHIu[A\ËHw[A\HǸHXHDUHATSHt7t8E1DJHsH{XIHIu[A\ËHw[A\HǸHXHDUHATSHt7t8E1DJHsH{XIHIu[A\ËHw[A\HǸHXHDUHAUATSHHtAtGHE1H8II JHsDH{XIHIu1H[A\A]ËHHwH8H HǸHXH1UHATSLHHwHXI$0HsH{XI$HsH{XI$[A\1UHATIStt1ۉLHHu[A\[A\UHATSLHHOM$0HyHqLLAH)HvDIQH)HDHsH{XI$HHsH{XI$`HsH{XI$ HsH{XI$HsH{XI$(HsH{XI$HsH{XI$HsH{XI$HsI$H{XM$HNHVH)H~AэI)CI$01HsH{XI$1HsH{XI$[A\1JIQHyHqLAH)H}JwHI)ȋIqUHATIStt1ۉLHHu[A\[A\UHAVAAUATISLWLMBIZIIMJL)HAL)A	H H	HHIIL)HLL)J	t\MILL)HLL)J	Eu,H"B	LL)HDHx;[A\A]A^1LL)J	1EADL)AT
\MT$I$I IrIzMJH)HLH)AJ	LH H	HHtiM4M0LH)HDˍI)BEu8HIKIrMJIzLH)H3DHHI|$IHILLLWLOHwL)MufL)эEMu1LL)Mu\AH)AA	fDύL),HL)ыH1LI)KH20H1LWHwLOoJ
J	MBMJIZCJ
UAHAWAAVIAUATSHGHHpHpHpHPH)Hx
AЉH)A8ỈE1I 1II	fHHt'LHLtDLHHAuEuSINMLAHqIpLHyL)HtfH:IRLAHqHyL)HuX[A\A]A^A_D[A\A]A^DA_HH)HIRL)HtH:D[A\A]A^A_ÐUHGXH@ DIHwH1HHPf.UIHEHD;3t	HHH(HHp3uH8w̉$LJLJLJA0ɺ
DLJA0	ɺDUHAWAVAAUATSHHL HMLWLOL_LL)M1DID$HHEL)M1DH(ljHHH	LMH	H0H	HHKH8LH	DLYHqH	ILAI L)HRD‰M~LL)H)BDHKMLHyHqLAH)H1DIQH)H1DHsH{XL1HsH{XLHsH{X1DILuBHCHML@HxLHL)HJ	M)ċKH[A\A]A^A_JBJHyLAHqDLDDJ8LYLAHqJJLWL_LOA	M)ĉC!ILL)HuDɍM)B1/LM)ƋKm_getzone10GbE SR10GbE LR10GbE LRM10GbE DA (Direct Attached)10GbE CX410GbE baseT10GbE Other1GbE SX1GbE LX1GbE CX1GbE baseT1GbE DA (Direct Attached)1GbE CX41GbE OtherUNSUPenabledisableL2 switch %s
change failed%d.%d.%d.%dx%d%sVPath(s)/function%s %d %sMSI-XINTA%d%luEnabledDisabledSingle PortDual Port%lldDriver version	: %s
Serial number	: %s
Part number	: %s
Firmware version	: %s
Firmware date	: %s
Link width	: %s
Function mode	: %s
Interrupt type	: %s
VPath(s) opened	: %s
Adapter Type	: %s
PMD Port 0	: %s
PMD Port 1	: %s
Port Mode	: %s
Port Failure	: %s
Active Port	: %s
L2 Switch	: %s
MTU is %s
LRO %s
RTH %s
TSO %s
Driver versionASerial numberPart numberFirmware versionFirmware dateLink widthFunction modeInterrupt typeVPath(s) openedAdapter Typepmd port 0pmd portpmd port 1Port ModePort FailureL2 SwitchLRO modeRTH modeTSO modesuccessfulfailedport mode change %s
dual port map change %s
function mode change %s
firmware upgrade %s
failed to reset vpath :%d
failed to create dma tags
failed to open vpath (%d)
LRO Initialization failed!
rth configuration failed
%s_drvnetwork driver%s_tx_%dActive Port : %lld
tx transfer code %d
adapter status: 0x%llx
hint.vxge.0.no_of_vpathhint.vxge.0.intr_coalescehint.vxge.0.rth_enablehint.vxge.0.rth_bkt_szhint.vxge.0.lro_enablehint.vxge.0.tso_enablehint.vxge.0.tx_steeringhint.vxge.0.msix_enablehint.vxge.0.ifqmaxlenhint.vxge.0.port_modehint.vxge.0.l2_switchhint.vxge.0.fw_upgradehint.vxge.0.low_latencyhint.vxge.0.func_modehint.vxge.0.bandwidth_%dhint.vxge.0.priority_%dfailed to initialize driver
setting mtu in device failed
failed to enable device
MTU changed to %ld
vxgeFailed to initialize driver
resource allocation failed
setting up interface failed
TSO Disabled
TSO Enabled
DefaultReservedActive/PassiveNo FailoverFailover onlyFailover & Failbackvxge_pcikernelpci/vxgepcivxgebus_dma_tag_create failed
bus_dmamem_alloc failed
vxgevxge%2.2d/%2.2d/%4.4d%d.%d.%d
Invalid port mode : %d
Exar Corp.X3100Fiber%d%s
TXDL %d : 0x%zx%d : 0x%zxWire Port Id : %s%c%u
alarm_transceiver_temp_highalarm_transceiver_temp_lowalarm_laser_bias_current_highalarm_laser_bias_current_lowalarm_laser_output_power_highalarm_laser_output_power_lowwarn_transceiver_temp_highwarn_transceiver_temp_lowwarn_laser_bias_current_highwarn_laser_bias_current_lowwarn_laser_output_power_highwarn_laser_output_power_lowmrpcim_alarmssrpcim_alarmsvpath_alarmsunknown_alarmsnetwork_sustained_faultnetwork_sustained_okkdfcctl_fifo0_overwritekdfcctl_fifo0_poisonkdfcctl_fifo0_dma_errorkdfcctl_fifo1_overwritekdfcctl_fifo1_poisonkdfcctl_fifo1_dma_errorkdfcctl_fifo2_overwritekdfcctl_fifo2_poisonkdfcctl_fifo2_dma_errordblgen_fifo0_overflowdblgen_fifo1_overflowdblgen_fifo2_overflowstatsb_pif_chain_errorstatsb_drop_timeouttarget_illegal_accessini_serr_detpci_config_status_errpci_config_uncor_errpci_config_cor_errmrpcim_to_vpath_alarmssrpcim_to_vpath_alarmssrpcim_msg_to_vpathprc_ring_bumpsprc_rxdcm_sc_errprc_rxdcm_sc_abortprc_quanta_size_errpic_ini_rd_droppic_ini_wr_droppic_ini_rd_vpin_droppic_ini_wr_vpin_droppic_genstats_count0pic_genstats_count1pic_genstats_count2pic_genstats_count3pic_genstats_count4pic_genstats_count5pci_rstdrop_cplpci_rstdrop_msgpci_rstdrop_client1pci_rstdrop_client0pci_rstdrop_client2pci_depl_cplh_vplane0pci_depl_nph_vplane0pci_depl_ph_vplane0pci_depl_cplh_vplane1pci_depl_nph_vplane1pci_depl_ph_vplane1pci_depl_cplh_vplane2pci_depl_nph_vplane2pci_depl_ph_vplane2pci_depl_cplh_vplane3pci_depl_nph_vplane3pci_depl_ph_vplane3pci_depl_cplh_vplane4pci_depl_nph_vplane4pci_depl_ph_vplane4pci_depl_cplh_vplane5pci_depl_nph_vplane5pci_depl_ph_vplane5pci_depl_cplh_vplane6pci_depl_nph_vplane6pci_depl_ph_vplane6pci_depl_cplh_vplane7pci_depl_nph_vplane7pci_depl_ph_vplane7pci_depl_cplh_vplane8pci_depl_nph_vplane8pci_depl_ph_vplane8pci_depl_cplh_vplane9pci_depl_nph_vplane9pci_depl_ph_vplane9pci_depl_cplh_vplane10pci_depl_nph_vplane10pci_depl_ph_vplane10pci_depl_cplh_vplane11pci_depl_nph_vplane11pci_depl_ph_vplane11pci_depl_cplh_vplane12pci_depl_nph_vplane12pci_depl_ph_vplane12pci_depl_cplh_vplane13pci_depl_nph_vplane13pci_depl_ph_vplane13pci_depl_cplh_vplane14pci_depl_nph_vplane14pci_depl_ph_vplane14pci_depl_cplh_vplane15pci_depl_nph_vplane15pci_depl_ph_vplane15pci_depl_cplh_vplane16pci_depl_nph_vplane16pci_depl_ph_vplane16pci_depl_cpld_vplane0pci_depl_npd_vplane0pci_depl_pd_vplane0pci_depl_cpld_vplane1pci_depl_npd_vplane1pci_depl_pd_vplane1pci_depl_cpld_vplane2pci_depl_npd_vplane2pci_depl_pd_vplane2pci_depl_cpld_vplane3pci_depl_npd_vplane3pci_depl_pd_vplane3pci_depl_cpld_vplane4pci_depl_npd_vplane4pci_depl_pd_vplane4pci_depl_cpld_vplane5pci_depl_npd_vplane5pci_depl_pd_vplane5pci_depl_cpld_vplane6pci_depl_npd_vplane6pci_depl_pd_vplane6pci_depl_cpld_vplane7pci_depl_npd_vplane7pci_depl_pd_vplane7pci_depl_cpld_vplane8pci_depl_npd_vplane8pci_depl_pd_vplane8pci_depl_cpld_vplane9pci_depl_npd_vplane9pci_depl_pd_vplane9pci_depl_cpld_vplane10pci_depl_npd_vplane10pci_depl_pd_vplane10pci_depl_cpld_vplane11pci_depl_npd_vplane11pci_depl_pd_vplane11pci_depl_cpld_vplane12pci_depl_npd_vplane12pci_depl_pd_vplane12pci_depl_cpld_vplane13pci_depl_npd_vplane13pci_depl_pd_vplane13pci_depl_cpld_vplane14pci_depl_npd_vplane14pci_depl_pd_vplane14pci_depl_cpld_vplane15pci_depl_npd_vplane15pci_depl_pd_vplane15pci_depl_cpld_vplane16pci_depl_npd_vplane16pci_depl_pd_vplane16tx_ttl_frms_PORT0%s%c%llu
tx_ttl_octets_PORT0tx_data_octets_PORT0tx_mcast_frms_PORT0tx_bcast_frms_PORT0tx_ucast_frms_PORT0tx_tagged_frms_PORT0tx_vld_ip_PORT0tx_vld_ip_octets_PORT0tx_icmp_PORT0tx_tcp_PORT0tx_rst_tcp_PORT0tx_udp_PORT0tx_parse_error_PORT0tx_unknown_protocol_PORT0tx_pause_ctrl_frms_PORT0tx_marker_pdu_frms_PORT0tx_lacpdu_frms_PORT0tx_drop_ip_PORT0tx_marker_resp_pdu_frms_PORT0tx_xgmii_char2_match_PORT0tx_xgmii_char1_match_PORT0tx_xgmii_column2_match_PORT0tx_xgmii_column1_match_PORT0tx_any_err_frms_PORT0tx_drop_frms_PORT0rx_ttl_frms_PORT0rx_vld_frms_PORT0rx_offload_frms_PORT0rx_ttl_octets_PORT0rx_data_octets_PORT0rx_offload_octets_PORT0rx_vld_mcast_frms_PORT0rx_vld_bcast_frms_PORT0rx_accepted_ucast_frms_PORT0rx_accepted_nucast_frms_PORT0rx_tagged_frms_PORT0rx_long_frms_PORT0rx_usized_frms_PORT0rx_osized_frms_PORT0rx_frag_frms_PORT0rx_jabber_frms_PORT0rx_ttl_64_frms_PORT0rx_ttl_65_127_frms_PORT0rx_ttl_128_255_frms_PORT0rx_ttl_256_511_frms_PORT0rx_ttl_512_1023_frms_PORT0rx_ttl_1024_1518_frms_PORT0rx_ttl_1519_4095_frms_PORT0rx_ttl_4096_8191_frms_PORT0rx_ttl_8192_max_frms_PORT0rx_ttl_gt_max_frms_PORT0rx_ip_PORT0rx_accepted_ip_PORT0rx_ip_octets_PORT0rx_err_ip_PORT0rx_icmp_PORT0rx_tcp_PORT0rx_udp_PORT0rx_err_tcp_PORT0rx_pause_cnt_PORT0rx_pause_ctrl_frms_PORT0rx_unsup_ctrl_frms_PORT0rx_fcs_err_frms_PORT0rx_in_rng_len_err_frms_PORT0rx_out_rng_len_err_frms_PORT0rx_drop_frms_PORT0rx_discarded_frms_PORT0rx_drop_ip_PORT0rx_drp_udp_PORT0rx_marker_pdu_frms_PORT0rx_lacpdu_frms_PORT0rx_unknown_pdu_frms_PORT0rx_marker_resp_pdu_frms_PORT0rx_fcs_discard_PORT0rx_illegal_pdu_frms_PORT0rx_switch_discard_PORT0rx_len_discard_PORT0rx_rpa_discard_PORT0rx_l2_mgmt_discard_PORT0rx_rts_discard_PORT0rx_trash_discard_PORT0rx_buff_full_discard_PORT0rx_red_discard_PORT0rx_xgmii_ctrl_err_cnt_PORT0rx_xgmii_data_err_cnt_PORT0rx_xgmii_char1_match_PORT0rx_xgmii_err_sym_PORT0rx_xgmii_column1_match_PORT0rx_xgmii_char2_match_PORT0rx_local_fault_PORT0rx_xgmii_column2_match_PORT0rx_jettison_PORT0rx_remote_fault_PORT0tx_ttl_frms_PORT1tx_ttl_octets_PORT1tx_data_octets_PORT1tx_mcast_frms_PORT1tx_bcast_frms_PORT1tx_ucast_frms_PORT1tx_tagged_frms_PORT1tx_vld_ip_PORT1tx_vld_ip_octets_PORT1tx_icmp_PORT1tx_tcp_PORT1tx_rst_tcp_PORT1tx_udp_PORT1tx_parse_error_PORT1tx_unknown_protocol_PORT1tx_pause_ctrl_frms_PORT1tx_marker_pdu_frms_PORT1tx_lacpdu_frms_PORT1tx_drop_ip_PORT1tx_marker_resp_pdu_frms_PORT1tx_xgmii_char2_match_PORT1tx_xgmii_char1_match_PORT1tx_xgmii_column2_match_PORT1tx_xgmii_column1_match_PORT1tx_any_err_frms_PORT1tx_drop_frms_PORT1rx_ttl_frms_PORT1rx_vld_frms_PORT1rx_offload_frms_PORT1rx_ttl_octets_PORT1rx_data_octets_PORT1rx_offload_octets_PORT1rx_vld_mcast_frms_PORT1rx_vld_bcast_frms_PORT1rx_accepted_ucast_frms_PORT1rx_accepted_nucast_frms_PORT1rx_tagged_frms_PORT1rx_long_frms_PORT1rx_usized_frms_PORT1rx_osized_frms_PORT1rx_frag_frms_PORT1rx_jabber_frms_PORT1rx_ttl_64_frms_PORT1rx_ttl_65_127_frms_PORT1rx_ttl_128_255_frms_PORT1rx_ttl_256_511_frms_PORT1rx_ttl_512_1023_frms_PORT1rx_ttl_1024_1518_frms_PORT1rx_ttl_1519_4095_frms_PORT1rx_ttl_4096_8191_frms_PORT1rx_ttl_8192_max_frms_PORT1rx_ttl_gt_max_frms_PORT1rx_ip_PORT1rx_accepted_ip_PORT1rx_ip_octets_PORT1rx_err_ip_PORT1rx_icmp_PORT1rx_tcp_PORT1rx_udp_PORT1rx_err_tcp_PORT1rx_pause_count_PORT1rx_pause_ctrl_frms_PORT1rx_unsup_ctrl_frms_PORT1rx_fcs_err_frms_PORT1rx_in_rng_len_err_frms_PORT1rx_out_rng_len_err_frms_PORT1rx_drop_frms_PORT1rx_discarded_frms_PORT1rx_drop_ip_PORT1rx_drop_udp_PORT1rx_marker_pdu_frms_PORT1rx_lacpdu_frms_PORT1rx_unknown_pdu_frms_PORT1rx_marker_resp_pdu_frms_PORT1rx_fcs_discard_PORT1rx_illegal_pdu_frms_PORT1rx_switch_discard_PORT1rx_len_discard_PORT1rx_rpa_discard_PORT1rx_l2_mgmt_discard_PORT1rx_rts_discard_PORT1rx_trash_discard_PORT1rx_buff_full_discard_PORT1rx_red_discard_PORT1rx_xgmii_ctrl_err_cnt_PORT1rx_xgmii_data_err_cnt_PORT1rx_xgmii_char1_match_PORT1rx_xgmii_err_sym_PORT1rx_xgmii_column1_match_PORT1rx_xgmii_char2_match_PORT1rx_local_fault_PORT1rx_xgmii_column2_match_PORT1rx_jettison_PORT1rx_remote_fault_PORT1tx_ttl_frms_PORT2tx_ttl_octets_PORT2tx_data_octets_PORT2tx_mcast_frms_PORT2tx_bcast_frms_PORT2tx_ucast_frms_PORT2tx_tagged_frms_PORT2tx_vld_ip_PORT2tx_vld_ip_octets_PORT2tx_icmp_PORT2tx_tcp_PORT2tx_rst_tcp_PORT2tx_udp_PORT2tx_parse_error_PORT2tx_unknown_protocol_PORT2tx_pause_ctrl_frms_PORT2tx_marker_pdu_frms_PORT2tx_lacpdu_frms_PORT2tx_drop_ip_PORT2tx_marker_resp_pdu_frms_PORT2tx_xgmii_char2_match_PORT2tx_xgmii_char1_match_PORT2tx_xgmii_column2_match_PORT2tx_xgmii_column1_match_PORT2tx_any_err_frms_PORT2tx_drop_frms_PORT2rx_ttl_frms_PORT2rx_vld_frms_PORT2rx_offload_frms_PORT2rx_ttl_octets_PORT2rx_data_octets_PORT2rx_offload_octets_PORT2rx_vld_mcast_frms_PORT2rx_vld_bcast_frms_PORT2rx_accepted_ucast_frms_PORT2rx_accepted_nucast_frms_PORT2rx_tagged_frms_PORT2rx_long_frms_PORT2rx_usized_frms_PORT2rx_osized_frms_PORT2rx_frag_frms_PORT2rx_jabber_frms_PORT2rx_ttl_64_frms_PORT2rx_ttl_65_127_frms_PORT2rx_ttl_128_255_frms_PORT2rx_ttl_256_511_frms_PORT2rx_ttl_512_1023_frms_PORT2rx_ttl_1024_1518_frms_PORT2rx_ttl_1519_4095_frms_PORT2rx_ttl_4096_8191_frms_PORT2rx_ttl_8192_max_frms_PORT2rx_ttl_gt_max_frms_PORT2rx_ip_PORT2rx_accepted_ip_PORT2rx_ip_octets_PORT2rx_err_ip_PORT2rx_icmp_PORT2rx_tcp_PORT2rx_udp_PORT2rx_err_tcp_PORT2rx_pause_count_PORT2rx_pause_ctrl_frms_PORT2rx_unsup_ctrl_frms_PORT2rx_fcs_err_frms_PORT2rx_in_rng_len_err_frms_PORT2rx_out_rng_len_err_frms_PORT2rx_drop_frms_PORT2rx_discarded_frms_PORT2rx_drop_ip_PORT2rx_drop_udp_PORT2rx_marker_pdu_frms_PORT2rx_lacpdu_frms_PORT2rx_unknown_pdu_frms_PORT2rx_marker_resp_pdu_frms_PORT2rx_fcs_discard_PORT2rx_illegal_pdu_frms_PORT2rx_switch_discard_PORT2rx_len_discard_PORT2rx_rpa_discard_PORT2rx_l2_mgmt_discard_PORT2rx_rts_discard_PORT2rx_trash_discard_PORT2rx_buff_full_discard_PORT2rx_red_discard_PORT2rx_xgmii_ctrl_err_cnt_PORT2rx_xgmii_data_err_cnt_PORT2rx_xgmii_char1_match_PORT2rx_xgmii_err_sym_PORT2rx_xgmii_column1_match_PORT2rx_xgmii_char2_match_PORT2rx_local_fault_PORT2rx_xgmii_column2_match_PORT2rx_jettison_PORT2rx_remote_fault_PORT2tx_frms_AGGR0tx_data_octets_AGGR0tx_mcast_frms_AGGR0tx_bcast_frms_AGGR0tx_discarded_frms_AGGR0tx_errored_frms_AGGR0rx_frms_AGGR0rx_data_octets_AGGR0rx_mcast_frms_AGGR0rx_bcast_frms_AGGR0rx_discarded_frms_AGGR0rx_errored_frms_AGGR0tx_frms_AGGR1tx_data_octets_AGGR1tx_mcast_frms_AGGR1tx_bcast_frms_AGGR1tx_discarded_frms_AGGR1tx_errored_frms_AGGR1rx_frms_AGGR1rx_data_octets_AGGR1rx_mcast_frms_AGGR1rx_bcast_frms_AGGR1rx_discarded_frms_AGGR1rx_errored_frms_AGGR1xgmac_global_prog_event_gnum0xgmac_global_prog_event_gnum1xgmac_orp_lro_eventsxgmac_orp_bs_eventsxgmac_orp_iwarp_eventsxgmac_tx_permitted_frmsxgmac_port2_tx_any_frmsxgmac_port1_tx_any_frmsxgmac_port0_tx_any_frmsxgmac_port2_rx_any_frmsxgmac_port1_rx_any_frmsxgmac_port0_rx_any_frmsring_full_cntring_usage_cntring_usage_maxring_avg_compl_per_intr_cntring_total_compl_cntrxd_t_code_err_cnt[%d]fifo_full_cntfifo_usage_cntfifo_usage_maxfifo_avg_compl_per_intr_cntfifo_total_compl_cnttotal_poststotal_buffersavg_buffers_per_postcopied_fragscopied_buffersavg_buffer_sizeavg_post_sizetotal_fragstotal_posts_dang_dtrstotal_posts_dang_fragstxd_t_code_err_cnt[%d]soft_reset_cntnot_traffic_intr_cnttraffic_intr_cnttotal_intr_cntS/W stats for vpath idini_num_mwr_sentini_num_mrd_sentini_num_cpl_rcvdini_num_mwr_byte_sentini_num_cpl_byte_rcvdwrcrdtarb_xoffrdcrdtarb_xoffvpath_genstats_count0vpath_genstats_count1vpath_genstats_count2vpath_genstats_count3vpath_genstats_count4vpath_genstats_count5tx_ttl_eth_frmstx_ttl_eth_octetstx_data_octetstx_mcast_frmstx_bcast_frmstx_ucast_frmstx_tagged_frmstx_vld_iptx_vld_ip_octetstx_icmptx_tcptx_rst_tcptx_udptx_unknown_protocoltx_lost_iptx_parse_errortx_tcp_offloadtx_retx_tcp_offloadtx_lost_ip_offloadrx_ttl_eth_frmsrx_vld_frmsrx_offload_frmsrx_ttl_eth_octetsrx_data_octetsrx_offload_octetsrx_vld_mcast_frmsrx_vld_bcast_frmsrx_accepted_ucast_frmsrx_accepted_nucast_frmsrx_tagged_frmsrx_long_frmsrx_usized_frmsrx_osized_frmsrx_frag_frmsrx_jabber_frmsrx_ttl_64_frmsrx_ttl_65_127_frmsrx_ttl_128_255_frmsrx_ttl_256_511_frmsrx_ttl_512_1023_frmsrx_ttl_1024_1518_frmsrx_ttl_1519_4095_frmsrx_ttl_4096_8191_frmsrx_ttl_8192_max_frmsrx_ttl_gt_max_frmsrx_iprx_accepted_iprx_ip_octetsrx_err_iprx_icmprx_tcprx_udprx_err_tcprx_lost_frmsrx_lost_iprx_lost_ip_offloadrx_various_discardrx_sleep_discardrx_red_discardrx_queue_full_discardrx_mpa_ok_frmsprog_event_vnum1prog_event_vnum0prog_event_vnum3prog_event_vnum2rx_multi_cast_frame_discardrx_frm_transferredrxd_returnedrx_mpa_len_fail_frmsrx_mpa_mrk_fail_frmsrx_mpa_crc_fail_frmsrx_permitted_frmsrx_vp_reset_discarded_frmsrx_wol_frmstx_vp_reset_discarded_frmsH/W stats for vpath id0x%04X%c0x%08X%08X
vendor_id%s%c0x%04X
device_idcommandstatusrevision%s%c0x%02X
pciClass1pciClass2pciClass3cache_line_sizeheader_typebistbase_addr0_lo%s%c0x%08X
base_addr0_hibase_addr1_lobase_addr1_hinot_Implemented1not_Implemented2cardbus_cis_pointersubsystem_vendor_idsubsystem_idrom_basecapabilities_pointerinterrupt_lineinterrupt_pinmin_grantmax_latencyPM Capabilitypm_cap_verpm_cap_pme_clockpm_cap_aux_powerpm_cap_dsipm_cap_aux_currentpm_cap_cap_d0pm_cap_cap_d1pm_cap_pme_d0pm_cap_pme_d1pm_cap_pme_d2pm_cap_pme_d3_hotpm_cap_pme_d3_coldpm_ctrl_statepm_ctrl_no_soft_resetpm_ctrl_pme_enablepm_ctrl_pme_data_selpm_ctrl_pme_data_scalepm_ctrl_pme_statuspm_ppb_ext_b2_b3pm_ppb_ext_ecc_enpm_data_regSID Capabilitysid_number_of_slotssid_first_in_chasissid_chasis_number%s%c0x%u
MSI CapabilityMSI EnableMSI 64bit Address CapableMSI PVM CapableMSI Vectors AllocatedMSI Max VectorsMSI address%s%c0x%016llX
%s%c0x%08llX
MSI DataMSI Mask bitsMSI Pending bitsMSIX CapabilityMSIX EnableMSIX Mask All vectorsMSIX Table SizeMSIX Table OffsetMSIX Table BIRMSIX PBA OffsetMSIX PBA BIRUnexpected CapabilityUnknown CapabilityDebug Levelvendor%s%c0x%x
devicesubsys_vendorsubsys_deviceboard_revvendor_name%s%c%s
chip_namemediahal_majorhal_minorhal_fixhal_buildll_majorll_minorll_fixll_build******* Legacy Reg **********0x%04x 0x%08x%08x
******* TOC Reg **************** Common Reg ***************** MRPCIM Reg **********FLASH DEFAULTDMA Block Pool size-MinimumDMA Block Pool size-InitialDMA Block Pool size-IncrementDMA Block Pool size-Maximumport_idmtuautoneg_modefixed_use_fsmantp_use_fsmanbe_use_fsmlink_stability_periodport_stability_periodtmac_enrmac_entmac_padtmac_pad_bytetmac_util_periodrmac_strip_fcsrmac_prom_enrmac_discard_pfrmrmac_util_periodrmac_pause_gen_enrmac_pause_rcv_enrmac_pause_timelimiter_enmax_limitnetwork_stability_periodmc_pause_threshold[i]tmac_perma_stop_entmac_tx_switch_distmac_lossy_switch_entmac_lossy_wire_entmac_bcast_to_wire_distmac_bcast_to_switch_distmac_host_append_fcs_entpa_support_snap_ab_ntpa_ecc_enable_nrpa_ignore_frame_errrpa_support_snap_ab_nrpa_search_for_haorpa_support_ipv6_mobile_hdrsrpa_ipv6_stop_searchingrpa_no_ps_if_unknownrpa_search_for_etyperpa_repl_l4_comp_csumrpa_repl_l3_incl_cfrpa_repl_l3_comp_csumrpa_repl_ipv4_tcp_incl_phrpa_repl_ipv6_tcp_incl_phrpa_repl_ipv4_udp_incl_phrpa_repl_ipv6_udp_incl_phrpa_repl_l4_incl_cfrpa_repl_strip_vlan_tagISR Polling countMaximum Payload SizeMMRB CountStatistics Refresh TimeInterrupt ModeDump on Unknwon ErrorDump on Serious ErrorDump on Critical ErrorDump on ECC ErrorRTH EnableRTS MAC EnableRTS QOS EnableRTS Port EnableMax CQE GroupsMax Number of OD GroupsNo WQE ThresholdRefill Threshold-HighRefill Threshold-LowAck Block LimitPoll or Doorbellstats_read_methodDevice Poll Timeoutdebug_leveldebug_maskVirtual Path idNo SnoopTPA LSOv2 EnableTPA Ignore Frame ErrorTPA IPv6 Keep SearchingTPA L4 pseudo header presentRPA L4 Include CFRPA Strip VLAN TagRPA L4 Comp Csum EnableRPA L3 Include CF EnableRPA L3 Comp CsumRPA Broadcast EnableRPA All VID EnableVP Queue L2 FlowRing blocksBuffer ModeScatter ModePost ModeMaximum Frame LengthNo Snoop BitsRx Timer ValueGreedy returnRx Timer CIBackoff IntervalIndicate Max PacketsFIFO BlocksMax FragsAlignment SizeMaximum Aligned FragsInterrupt EnableBTimer ValueTimer AC EnableTimer CI EnableTimer RI EnableTimer Event SFRTimer ValueUtil SelLTimer ValueTx Frame Count EnableTxd Count EnableUtil Range AUtil Event Count AUtil Range BUtil Event Count BUtil Range CUtil Event Count CUtil Event Count DUfca Interrupt ThresholdUfca Low LimitUfca High LimitUfca lbolt period10 Gigabit Ethernet Adapternot availableNo vpaths available in device
Upgrade driver through vxge_update, Unable to load the driver.
For optimal performance a x8 PCI-Express slot is required.
vendor=??, sn=??, pn=??, type=??vendor=%s, sn=%s, pn=%s, type=%sSingle Function - 1 function(s)Multi Function - 2 function(s)Multi Function - 4 function(s)Multi Function - 8 function(s)Multi Function (DirectIO) - 8 function(s)port behaviour on failure change %s
Adapter in SF mode, dual port mode is not allowed
Current firmware version : %s (%s)
Upgrading firmware to %d.%d.%d
PLEASE POWER CYCLE THE SYSTEM
rth configuration failed for vpath (%d)
Unable to allocate msi/x vectors switching to INTA mode
failed to allocate line interrupt resource
allocating bus resource (rid %d) failed
failed to allocate memory for bus resources
failed to allocate memory bar resources
failed to set msix vectors to vpath
processing alarms urecoverable error %x
memory allocation for ifnet failed
%s: m_getjcl: invalid cluster typeout of memory to allocate mbuf
/usr/src/sys/modules/vxge/../../dev/vxge/vxge.cFailed to load driver, 		    invalid config : 'no_of_vpath'
invalid mtu size %ld specified
can't enable bcast on vpath (%d)
Neterion x3100 10GbE PCIe Server Adapter (Rev %d)Copyright(c) 2002-2011 Exar Corp.
failed to allocate memory for pci info
failed to allocate memory for device config
isr resource allocation failed
hal device initialization failed
failed to associate interrupt handler with device
vpath memory allocation failed
failed pciconfig statistics query
failed mrpcim statistics query
failed device statistics query
failed device hardware info query
failed driver statistics query
Enable tx checksum offload 					     first.
/usr/src/sys/modules/vxge/../../dev/vxge/vxgehal/vxge-queue.c/usr/src/sys/modules/vxge/../../dev/vxge/vxgehal/vxgehal-fifo.c/usr/src/sys/modules/vxge/../../dev/vxge/vxgehal/vxgehal-ring.cInvalid setting for failure behavior : %d
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******* VPATH MGMT Reg : %d **********
******* VPATH Reg : %d **********
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charVXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTOlock_objectv_swapinv_page_sizedevice_shutdown_descVXGE_HAL_BADCFG_UMQ_GEN_COMPLVXGE_HAL_BADCFG_LRO_ACK_NBR_DELTAvnet_ifcntpci_set_powerstate_descVXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SELVXGE_HAL_BADCFG_RING_ENABLEcrit_errVXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIODv_inactive_countM_databufVXGE_HAL_BADCFG_ISR_POLLING_CNTVXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUMif_dnamemh_nextmh_dataVXGE_HAL_BADCFG_DUMP_ON_UNKNOWNVXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPEtime_tref_cntVXGE_HAL_BADCFG_STATS_REFRESH_TIMEifgm_nextif_vlantrunkVXGE_HAL_ERR_XGMAC_X_PLL_IN_LOCKif_labelMH_datif_outputwitnessv_free_severeta_pendingpci_enable_busmaster_descVXGE_HAL_BADCFG_LAG_PREF_INDIV_PORTVXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIMEVXGE_TRACEVXGE_HAL_EVENT_MRPCIM_CRITICALVXGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENTv_swtchVXGE_HAL_ERR_SPDM_NOT_ENABLEDVXGE_HAL_INF_OUT_OF_DESCRIPTORSVXGE_HAL_COMPLETIONS_REMAINVXGE_HAL_ERR_INVALID_BANDWIDTH_LIMITv_cache_maxVXGE_HAL_INF_SW_LRO_BEGINifi_collisionsVXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAGks_shortdescpci_assign_interrupt_descifg_refcntVXGE_HAL_ERR_EVENT_UNKNOWNVXGE_HAL_ERR_MANAGER_NOT_FOUNDaltq_cdnrifpr_prefixVXGE_HAL_ERR_EVENT_SRPCIM_CRITICALVXGE_HAL_BADCFG_LOG_LEVELv_tcachedv_cow_faultsVXGE_HAL_BADCFG_VPATH_QOS_PRIORITYVXGE_HAL_INF_SW_LRO_UNCAPABLEext_typeVXGE_HAL_BADCFG_LAG_AGGR_AGGR_IDif_linkmibVXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN__uint8_tVXGE_HAL_INF_MEM_STROBE_CMD_EXECUTINGVXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_ENVXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIAVXGE_HAL_ERR_EVENT_MRPCIM_CRITICALVXGE_HAL_BADCFG_TIM_TIMER_CI_ENvxge_hal_status_eVXGE_HAL_ERR_BAD_DEVICE_IDvxge_uld_link_up_fVXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHINGVXGE_HAL_ERR_INVALID_DP_MODEVXGE_HAL_PENDINGVXGE_HAL_BADCFG_VPATH_MTUVXGE_HAL_BADCFG_LRO_SESSION_ECNVXGE_HAL_ERR_PKT_DROPVXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTINGVXGE_HAL_ERR_INVALID_TYPEVXGE_HAL_INF_SW_LRO_FLUSH_SESSIONv_vnodeinv_ozfodVXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PHVXGE_HAL_ERR_INVALID_TCODElong intVXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_ENVXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DISVXGE_HAL_BADCFG_RTH_ENVXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATEu_int16_tVXGE_HAL_ERR_ROCRC_RC_PRC_QUIESCENTsched_timerv_interrupt_free_minVXGE_HAL_ERR_INVALID_WIRE_PORTVXGE_HAL_BADCFG_LRO_DUPACK_DETECTIONzone_packifi_metricif_afdata_lockg_vxge_hal_driverVXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1Gbus_probe_nomatch_descVXGE_HAL_ERR_KDFC_KDFC_READYVXGE_HAL_ERR_VPATH_NOT_AVAILABLEVXGE_HAL_ERR_INVALID_TOTAL_BANDWIDTHVXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_ENVXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALLVXGE_HAL_BADCFG_LAG_HOT_STANDBYVXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_ENVXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIODVXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_ENvnet_data_memVXGE_HAL_ERR_OUT_OF_MAC_ADDRESSESVXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10GVXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PHVXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEYks_magicbus_teardown_intr_desckobjop_tVXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTINGifmultiaddrVXGE_HAL_BADCFG_RING_MAX_FRM_LENrt_addrinfoVXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRIVXGE_HAL_BADCFG_VPATH_TPA_LSOV2_ENVXGE_HAL_OKVXGE_HAL_BADCFG_LAG_LONG_TIMEOUTVXGE_HAL_BADCFG_TIM_RTIMER_VALsle_nextVXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PHVXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERRORVXGE_HAL_BADCFG_LAG_MARKER_RESP_ENuint8_tVXGE_HAL_BADCFG_LRO_SCATTER_MODEVXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMITVXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITYifprefixheadif_clonesVXGE_HAL_BADCFG_VPATH_RPA_CAST_ENifma_llifmata_funcVXGE_HAL_ERR_WRONG_IRQVXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRMkobj_methodunsigned charpci_disable_busmaster_descv_reactivatedif_fibVXGE_HAL_ERR_G3IF_FB_G3IF_FB_GDDR3_READYta_linkvmmeterVXGE_HAL_ERR_INVALID_INDEXvxge_hal_event_eVXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTEVXGE_HAL_BADCFG_RING_LENGTHlink_upcsum_flagsGNU C 4.2.1 20070831 patched [FreeBSD]ifq_lenpci_release_msi_descbus_new_pass_descif_softcvxge_hal_xpak_alarm_type_eVXGE_HAL_EVENT_DEVICE_RESET_STARTVXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUMheaderdefltif_linkks_handleVXGE_HAL_ERR_INVALID_L2_SWITCH_STATE_BoolVXGE_HAL_BADCFG_TIM_UEC_AVXGE_HAL_BADCFG_TIM_UEC_BVXGE_HAL_BADCFG_TIM_UEC_CVXGE_HAL_BADCFG_TIM_UEC_DVXGE_HAL_EVENT_ECCERRifaddrheadu_int8_tvxge_uld_xpak_alarm_log_fVXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_ENVXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUTzone_jumbo9pkthdrcharVXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DISbus_write_ivar_descVXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGRext_freezone_clustVXGE_HAL_BADCFG_RTS_QOS_ENVXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSMv_vnodeoutvnet_data_baseifi_noprotom_tagVXGE_HAL_EVENT_VPATH_RESET_STARTVXGE_HAL_INF_SW_LRO_END_3VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTUmalloc_typemh_flagsVXGE_HAL_ERR_ROCRC_OFFLOAD_QUIESCENT__uint16_tVXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATIONifq_drv_headVXGE_HAL_BADCFG_LRO_FRAME_THRESHOLDtimevalzone_jumboplong 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intif_transmittbr_tokenVXGE_HAL_RETURNif_prefixheadbus_hinted_child_desc__sa_family_tbus_adjust_resource_descstatusif_alloctypem_tag_lenVXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PHVXGE_HAL_ERR_INVALID_MAX_BANDWIDTHVXGE_HAL_ERR_CRITICALbif_nextvxge_hal_driver_debug_getVXGE_HAL_BADCFG_FIFO_FRAGSVXGE_HAL_BADCFG_LRO_IP_DATAGRAM_SIZEVXGE_HAL_ERR_SPDM_TABLE_FULLVXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SFm_tag_freezone_mbufVXGE_HAL_BADCFG_SW_LRO_SESSIONSVXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CFVXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIODVXGE_HAL_EOF_TRACE_BUFVXGE_ERRv_softVXGE_HAL_ERR_RTDMA_RTDMA_READYVXGE_HAL_ERR_DRIVER_NOT_INITIALIZEDVXGE_HAL_BADCFG_RING_GREEDY_RETURNifgl_nextv_pdwakeupsbus_read_ivar_desctop_cdnrVXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWNpci_write_config_descif_ioctltbr_filluptimevnet_magic_nbus_hint_device_unit_descVXGE_HAL_BADCFG_MSIX_IDVXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORSVXGE_HAL_ERR_SLOT_FREEZEbus_release_resource_descv_inactive_targetbus_print_child_descVXGE_HAL_BADCFG_LAG_FAILBACK_ENifma_linkVXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIODrw_lockifi_ipacketsVXGE_HAL_ERR_INVALID_MAC_ADDRESSVXGE_HAL_ERR_INVALID_MIN_BANDWIDTHVXGE_HAL_ERR_RESET_FAILEDVXGE_HAL_BADCFG_FIFO_MAX_FRAGSVXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTEDVXGE_HAL_INF_NOT_ENOUGH_HW_CQESVXGE_HAL_BADCFG_UFCA_LO_LIMVXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMITvxge_hal_uld_cbs_tifma_protospecVXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALEifa_metriclo_flagsVXGE_HAL_BADCFG_LAG_LACP_BEGINdevice_probe_descif_afdata_initializedifma_lladdrVXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_USVXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_ENif_llsoftc__uint32_tVXGE_HAL_BADCFG_LRO_SESSION_ECN_NONCEif_initVXGE_HAL_BADCFG_RTH_IT_TYPEVXGE_HAL_XPAK_ALARM_EXCESS_TEMPtso_segszlong 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