| Current Path : /usr/local/lib/perl5/site_perl/5.8.9/mach/machine/ |
FreeBSD hs32.drive.ne.jp 9.1-RELEASE FreeBSD 9.1-RELEASE #1: Wed Jan 14 12:18:08 JST 2015 root@hs32.drive.ne.jp:/sys/amd64/compile/hs32 amd64 |
| Current File : //usr/local/lib/perl5/site_perl/5.8.9/mach/machine/specialreg.ph |
require '_h2ph_pre.ph';
no warnings 'redefine';
unless(defined(&_MACHINE_SPECIALREG_H_)) {
eval 'sub _MACHINE_SPECIALREG_H_ () {1;}' unless defined(&_MACHINE_SPECIALREG_H_);
eval 'sub CR0_PE () {0x1;}' unless defined(&CR0_PE);
eval 'sub CR0_MP () {0x2;}' unless defined(&CR0_MP);
eval 'sub CR0_EM () {0x4;}' unless defined(&CR0_EM);
eval 'sub CR0_TS () {0x8;}' unless defined(&CR0_TS);
eval 'sub CR0_PG () {0x80000000;}' unless defined(&CR0_PG);
eval 'sub CR0_NE () {0x20;}' unless defined(&CR0_NE);
eval 'sub CR0_WP () {0x10000;}' unless defined(&CR0_WP);
eval 'sub CR0_AM () {0x40000;}' unless defined(&CR0_AM);
eval 'sub CR0_NW () {0x20000000;}' unless defined(&CR0_NW);
eval 'sub CR0_CD () {0x40000000;}' unless defined(&CR0_CD);
eval 'sub CR4_VME () {0x1;}' unless defined(&CR4_VME);
eval 'sub CR4_PVI () {0x2;}' unless defined(&CR4_PVI);
eval 'sub CR4_TSD () {0x4;}' unless defined(&CR4_TSD);
eval 'sub CR4_DE () {0x8;}' unless defined(&CR4_DE);
eval 'sub CR4_PSE () {0x10;}' unless defined(&CR4_PSE);
eval 'sub CR4_PAE () {0x20;}' unless defined(&CR4_PAE);
eval 'sub CR4_MCE () {0x40;}' unless defined(&CR4_MCE);
eval 'sub CR4_PGE () {0x80;}' unless defined(&CR4_PGE);
eval 'sub CR4_PCE () {0x100;}' unless defined(&CR4_PCE);
eval 'sub CR4_FXSR () {0x200;}' unless defined(&CR4_FXSR);
eval 'sub CR4_XMM () {0x400;}' unless defined(&CR4_XMM);
eval 'sub CR4_XSAVE () {0x40000;}' unless defined(&CR4_XSAVE);
eval 'sub EFER_SCE () {0x1;}' unless defined(&EFER_SCE);
eval 'sub EFER_LME () {0x100;}' unless defined(&EFER_LME);
eval 'sub EFER_LMA () {0x400;}' unless defined(&EFER_LMA);
eval 'sub EFER_NXE () {0x800;}' unless defined(&EFER_NXE);
eval 'sub XCR0 () {0;}' unless defined(&XCR0);
eval 'sub XFEATURE_ENABLED_X87 () {0x1;}' unless defined(&XFEATURE_ENABLED_X87);
eval 'sub XFEATURE_ENABLED_SSE () {0x2;}' unless defined(&XFEATURE_ENABLED_SSE);
eval 'sub XFEATURE_ENABLED_AVX () {0x4;}' unless defined(&XFEATURE_ENABLED_AVX);
eval 'sub XFEATURE_AVX () {( &XFEATURE_ENABLED_X87 | &XFEATURE_ENABLED_SSE | &XFEATURE_ENABLED_AVX);}' unless defined(&XFEATURE_AVX);
eval 'sub CPUID_FPU () {0x1;}' unless defined(&CPUID_FPU);
eval 'sub CPUID_VME () {0x2;}' unless defined(&CPUID_VME);
eval 'sub CPUID_DE () {0x4;}' unless defined(&CPUID_DE);
eval 'sub CPUID_PSE () {0x8;}' unless defined(&CPUID_PSE);
eval 'sub CPUID_TSC () {0x10;}' unless defined(&CPUID_TSC);
eval 'sub CPUID_MSR () {0x20;}' unless defined(&CPUID_MSR);
eval 'sub CPUID_PAE () {0x40;}' unless defined(&CPUID_PAE);
eval 'sub CPUID_MCE () {0x80;}' unless defined(&CPUID_MCE);
eval 'sub CPUID_CX8 () {0x100;}' unless defined(&CPUID_CX8);
eval 'sub CPUID_APIC () {0x200;}' unless defined(&CPUID_APIC);
eval 'sub CPUID_B10 () {0x400;}' unless defined(&CPUID_B10);
eval 'sub CPUID_SEP () {0x800;}' unless defined(&CPUID_SEP);
eval 'sub CPUID_MTRR () {0x1000;}' unless defined(&CPUID_MTRR);
eval 'sub CPUID_PGE () {0x2000;}' unless defined(&CPUID_PGE);
eval 'sub CPUID_MCA () {0x4000;}' unless defined(&CPUID_MCA);
eval 'sub CPUID_CMOV () {0x8000;}' unless defined(&CPUID_CMOV);
eval 'sub CPUID_PAT () {0x10000;}' unless defined(&CPUID_PAT);
eval 'sub CPUID_PSE36 () {0x20000;}' unless defined(&CPUID_PSE36);
eval 'sub CPUID_PSN () {0x40000;}' unless defined(&CPUID_PSN);
eval 'sub CPUID_CLFSH () {0x80000;}' unless defined(&CPUID_CLFSH);
eval 'sub CPUID_B20 () {0x100000;}' unless defined(&CPUID_B20);
eval 'sub CPUID_DS () {0x200000;}' unless defined(&CPUID_DS);
eval 'sub CPUID_ACPI () {0x400000;}' unless defined(&CPUID_ACPI);
eval 'sub CPUID_MMX () {0x800000;}' unless defined(&CPUID_MMX);
eval 'sub CPUID_FXSR () {0x1000000;}' unless defined(&CPUID_FXSR);
eval 'sub CPUID_SSE () {0x2000000;}' unless defined(&CPUID_SSE);
eval 'sub CPUID_XMM () {0x2000000;}' unless defined(&CPUID_XMM);
eval 'sub CPUID_SSE2 () {0x4000000;}' unless defined(&CPUID_SSE2);
eval 'sub CPUID_SS () {0x8000000;}' unless defined(&CPUID_SS);
eval 'sub CPUID_HTT () {0x10000000;}' unless defined(&CPUID_HTT);
eval 'sub CPUID_TM () {0x20000000;}' unless defined(&CPUID_TM);
eval 'sub CPUID_IA64 () {0x40000000;}' unless defined(&CPUID_IA64);
eval 'sub CPUID_PBE () {0x80000000;}' unless defined(&CPUID_PBE);
eval 'sub CPUID2_SSE3 () {0x1;}' unless defined(&CPUID2_SSE3);
eval 'sub CPUID2_PCLMULQDQ () {0x2;}' unless defined(&CPUID2_PCLMULQDQ);
eval 'sub CPUID2_DTES64 () {0x4;}' unless defined(&CPUID2_DTES64);
eval 'sub CPUID2_MON () {0x8;}' unless defined(&CPUID2_MON);
eval 'sub CPUID2_DS_CPL () {0x10;}' unless defined(&CPUID2_DS_CPL);
eval 'sub CPUID2_VMX () {0x20;}' unless defined(&CPUID2_VMX);
eval 'sub CPUID2_SMX () {0x40;}' unless defined(&CPUID2_SMX);
eval 'sub CPUID2_EST () {0x80;}' unless defined(&CPUID2_EST);
eval 'sub CPUID2_TM2 () {0x100;}' unless defined(&CPUID2_TM2);
eval 'sub CPUID2_SSSE3 () {0x200;}' unless defined(&CPUID2_SSSE3);
eval 'sub CPUID2_CNXTID () {0x400;}' unless defined(&CPUID2_CNXTID);
eval 'sub CPUID2_FMA () {0x1000;}' unless defined(&CPUID2_FMA);
eval 'sub CPUID2_CX16 () {0x2000;}' unless defined(&CPUID2_CX16);
eval 'sub CPUID2_XTPR () {0x4000;}' unless defined(&CPUID2_XTPR);
eval 'sub CPUID2_PDCM () {0x8000;}' unless defined(&CPUID2_PDCM);
eval 'sub CPUID2_PCID () {0x20000;}' unless defined(&CPUID2_PCID);
eval 'sub CPUID2_DCA () {0x40000;}' unless defined(&CPUID2_DCA);
eval 'sub CPUID2_SSE41 () {0x80000;}' unless defined(&CPUID2_SSE41);
eval 'sub CPUID2_SSE42 () {0x100000;}' unless defined(&CPUID2_SSE42);
eval 'sub CPUID2_X2APIC () {0x200000;}' unless defined(&CPUID2_X2APIC);
eval 'sub CPUID2_MOVBE () {0x400000;}' unless defined(&CPUID2_MOVBE);
eval 'sub CPUID2_POPCNT () {0x800000;}' unless defined(&CPUID2_POPCNT);
eval 'sub CPUID2_TSCDLT () {0x1000000;}' unless defined(&CPUID2_TSCDLT);
eval 'sub CPUID2_AESNI () {0x2000000;}' unless defined(&CPUID2_AESNI);
eval 'sub CPUID2_XSAVE () {0x4000000;}' unless defined(&CPUID2_XSAVE);
eval 'sub CPUID2_OSXSAVE () {0x8000000;}' unless defined(&CPUID2_OSXSAVE);
eval 'sub CPUID2_AVX () {0x10000000;}' unless defined(&CPUID2_AVX);
eval 'sub CPUID2_F16C () {0x20000000;}' unless defined(&CPUID2_F16C);
eval 'sub CPUID2_RDRAND () {0x40000000;}' unless defined(&CPUID2_RDRAND);
eval 'sub CPUID2_HV () {0x80000000;}' unless defined(&CPUID2_HV);
eval 'sub CPUTPM1_SENSOR () {0x1;}' unless defined(&CPUTPM1_SENSOR);
eval 'sub CPUTPM1_TURBO () {0x2;}' unless defined(&CPUTPM1_TURBO);
eval 'sub CPUTPM1_ARAT () {0x4;}' unless defined(&CPUTPM1_ARAT);
eval 'sub CPUTPM2_EFFREQ () {0x1;}' unless defined(&CPUTPM2_EFFREQ);
eval 'sub AMDID_SYSCALL () {0x800;}' unless defined(&AMDID_SYSCALL);
eval 'sub AMDID_MP () {0x80000;}' unless defined(&AMDID_MP);
eval 'sub AMDID_NX () {0x100000;}' unless defined(&AMDID_NX);
eval 'sub AMDID_EXT_MMX () {0x400000;}' unless defined(&AMDID_EXT_MMX);
eval 'sub AMDID_FFXSR () {0x1000000;}' unless defined(&AMDID_FFXSR);
eval 'sub AMDID_PAGE1GB () {0x4000000;}' unless defined(&AMDID_PAGE1GB);
eval 'sub AMDID_RDTSCP () {0x8000000;}' unless defined(&AMDID_RDTSCP);
eval 'sub AMDID_LM () {0x20000000;}' unless defined(&AMDID_LM);
eval 'sub AMDID_EXT_3DNOW () {0x40000000;}' unless defined(&AMDID_EXT_3DNOW);
eval 'sub AMDID_3DNOW () {0x80000000;}' unless defined(&AMDID_3DNOW);
eval 'sub AMDID2_LAHF () {0x1;}' unless defined(&AMDID2_LAHF);
eval 'sub AMDID2_CMP () {0x2;}' unless defined(&AMDID2_CMP);
eval 'sub AMDID2_SVM () {0x4;}' unless defined(&AMDID2_SVM);
eval 'sub AMDID2_EXT_APIC () {0x8;}' unless defined(&AMDID2_EXT_APIC);
eval 'sub AMDID2_CR8 () {0x10;}' unless defined(&AMDID2_CR8);
eval 'sub AMDID2_ABM () {0x20;}' unless defined(&AMDID2_ABM);
eval 'sub AMDID2_SSE4A () {0x40;}' unless defined(&AMDID2_SSE4A);
eval 'sub AMDID2_MAS () {0x80;}' unless defined(&AMDID2_MAS);
eval 'sub AMDID2_PREFETCH () {0x100;}' unless defined(&AMDID2_PREFETCH);
eval 'sub AMDID2_OSVW () {0x200;}' unless defined(&AMDID2_OSVW);
eval 'sub AMDID2_IBS () {0x400;}' unless defined(&AMDID2_IBS);
eval 'sub AMDID2_XOP () {0x800;}' unless defined(&AMDID2_XOP);
eval 'sub AMDID2_SKINIT () {0x1000;}' unless defined(&AMDID2_SKINIT);
eval 'sub AMDID2_WDT () {0x2000;}' unless defined(&AMDID2_WDT);
eval 'sub AMDID2_LWP () {0x8000;}' unless defined(&AMDID2_LWP);
eval 'sub AMDID2_FMA4 () {0x10000;}' unless defined(&AMDID2_FMA4);
eval 'sub AMDID2_NODE_ID () {0x80000;}' unless defined(&AMDID2_NODE_ID);
eval 'sub AMDID2_TBM () {0x200000;}' unless defined(&AMDID2_TBM);
eval 'sub AMDID2_TOPOLOGY () {0x400000;}' unless defined(&AMDID2_TOPOLOGY);
eval 'sub CPUID_STEPPING () {0xf;}' unless defined(&CPUID_STEPPING);
eval 'sub CPUID_MODEL () {0xf0;}' unless defined(&CPUID_MODEL);
eval 'sub CPUID_FAMILY () {0xf00;}' unless defined(&CPUID_FAMILY);
eval 'sub CPUID_EXT_MODEL () {0xf0000;}' unless defined(&CPUID_EXT_MODEL);
eval 'sub CPUID_EXT_FAMILY () {0xff00000;}' unless defined(&CPUID_EXT_FAMILY);
eval 'sub CPUID_TO_MODEL {
my($id) = @_;
eval q((((($id) & &CPUID_MODEL) >> 4) | ((($id) & &CPUID_EXT_MODEL) >> 12)));
}' unless defined(&CPUID_TO_MODEL);
eval 'sub CPUID_TO_FAMILY {
my($id) = @_;
eval q((((($id) & &CPUID_FAMILY) >> 8) + ((($id) & &CPUID_EXT_FAMILY) >> 20)));
}' unless defined(&CPUID_TO_FAMILY);
eval 'sub CPUID_BRAND_INDEX () {0xff;}' unless defined(&CPUID_BRAND_INDEX);
eval 'sub CPUID_CLFUSH_SIZE () {0xff00;}' unless defined(&CPUID_CLFUSH_SIZE);
eval 'sub CPUID_HTT_CORES () {0xff0000;}' unless defined(&CPUID_HTT_CORES);
eval 'sub CPUID_LOCAL_APIC_ID () {0xff000000;}' unless defined(&CPUID_LOCAL_APIC_ID);
eval 'sub CPUID_PERF_STAT () {0x1;}' unless defined(&CPUID_PERF_STAT);
eval 'sub CPUID_PERF_BIAS () {0x8;}' unless defined(&CPUID_PERF_BIAS);
eval 'sub CPUID_TYPE_INVAL () {0;}' unless defined(&CPUID_TYPE_INVAL);
eval 'sub CPUID_TYPE_SMT () {1;}' unless defined(&CPUID_TYPE_SMT);
eval 'sub CPUID_TYPE_CORE () {2;}' unless defined(&CPUID_TYPE_CORE);
eval 'sub AMDPM_TS () {0x1;}' unless defined(&AMDPM_TS);
eval 'sub AMDPM_FID () {0x2;}' unless defined(&AMDPM_FID);
eval 'sub AMDPM_VID () {0x4;}' unless defined(&AMDPM_VID);
eval 'sub AMDPM_TTP () {0x8;}' unless defined(&AMDPM_TTP);
eval 'sub AMDPM_TM () {0x10;}' unless defined(&AMDPM_TM);
eval 'sub AMDPM_STC () {0x20;}' unless defined(&AMDPM_STC);
eval 'sub AMDPM_100MHZ_STEPS () {0x40;}' unless defined(&AMDPM_100MHZ_STEPS);
eval 'sub AMDPM_HW_PSTATE () {0x80;}' unless defined(&AMDPM_HW_PSTATE);
eval 'sub AMDPM_TSC_INVARIANT () {0x100;}' unless defined(&AMDPM_TSC_INVARIANT);
eval 'sub AMDPM_CPB () {0x200;}' unless defined(&AMDPM_CPB);
eval 'sub AMDID_CMP_CORES () {0xff;}' unless defined(&AMDID_CMP_CORES);
eval 'sub AMDID_COREID_SIZE () {0xf000;}' unless defined(&AMDID_COREID_SIZE);
eval 'sub AMDID_COREID_SIZE_SHIFT () {12;}' unless defined(&AMDID_COREID_SIZE_SHIFT);
eval 'sub AMD_VENDOR_ID () {"AuthenticAMD";}' unless defined(&AMD_VENDOR_ID);
eval 'sub CENTAUR_VENDOR_ID () {"CentaurHauls";}' unless defined(&CENTAUR_VENDOR_ID);
eval 'sub INTEL_VENDOR_ID () {"GenuineIntel";}' unless defined(&INTEL_VENDOR_ID);
eval 'sub MSR_P5_MC_ADDR () {0x;}' unless defined(&MSR_P5_MC_ADDR);
eval 'sub MSR_P5_MC_TYPE () {0x1;}' unless defined(&MSR_P5_MC_TYPE);
eval 'sub MSR_TSC () {0x10;}' unless defined(&MSR_TSC);
eval 'sub MSR_P5_CESR () {0x11;}' unless defined(&MSR_P5_CESR);
eval 'sub MSR_P5_CTR0 () {0x12;}' unless defined(&MSR_P5_CTR0);
eval 'sub MSR_P5_CTR1 () {0x13;}' unless defined(&MSR_P5_CTR1);
eval 'sub MSR_IA32_PLATFORM_ID () {0x17;}' unless defined(&MSR_IA32_PLATFORM_ID);
eval 'sub MSR_APICBASE () {0x1b;}' unless defined(&MSR_APICBASE);
eval 'sub MSR_EBL_CR_POWERON () {0x2a;}' unless defined(&MSR_EBL_CR_POWERON);
eval 'sub MSR_TEST_CTL () {0x33;}' unless defined(&MSR_TEST_CTL);
eval 'sub MSR_BIOS_UPDT_TRIG () {0x79;}' unless defined(&MSR_BIOS_UPDT_TRIG);
eval 'sub MSR_BBL_CR_D0 () {0x88;}' unless defined(&MSR_BBL_CR_D0);
eval 'sub MSR_BBL_CR_D1 () {0x89;}' unless defined(&MSR_BBL_CR_D1);
eval 'sub MSR_BBL_CR_D2 () {0x8a;}' unless defined(&MSR_BBL_CR_D2);
eval 'sub MSR_BIOS_SIGN () {0x8b;}' unless defined(&MSR_BIOS_SIGN);
eval 'sub MSR_PERFCTR0 () {0xc1;}' unless defined(&MSR_PERFCTR0);
eval 'sub MSR_PERFCTR1 () {0xc2;}' unless defined(&MSR_PERFCTR1);
eval 'sub MSR_MPERF () {0xe7;}' unless defined(&MSR_MPERF);
eval 'sub MSR_APERF () {0xe8;}' unless defined(&MSR_APERF);
eval 'sub MSR_IA32_EXT_CONFIG () {0xee;}' unless defined(&MSR_IA32_EXT_CONFIG);
eval 'sub MSR_MTRRcap () {0xfe;}' unless defined(&MSR_MTRRcap);
eval 'sub MSR_BBL_CR_ADDR () {0x116;}' unless defined(&MSR_BBL_CR_ADDR);
eval 'sub MSR_BBL_CR_DECC () {0x118;}' unless defined(&MSR_BBL_CR_DECC);
eval 'sub MSR_BBL_CR_CTL () {0x119;}' unless defined(&MSR_BBL_CR_CTL);
eval 'sub MSR_BBL_CR_TRIG () {0x11a;}' unless defined(&MSR_BBL_CR_TRIG);
eval 'sub MSR_BBL_CR_BUSY () {0x11b;}' unless defined(&MSR_BBL_CR_BUSY);
eval 'sub MSR_BBL_CR_CTL3 () {0x11e;}' unless defined(&MSR_BBL_CR_CTL3);
eval 'sub MSR_SYSENTER_CS_MSR () {0x174;}' unless defined(&MSR_SYSENTER_CS_MSR);
eval 'sub MSR_SYSENTER_ESP_MSR () {0x175;}' unless defined(&MSR_SYSENTER_ESP_MSR);
eval 'sub MSR_SYSENTER_EIP_MSR () {0x176;}' unless defined(&MSR_SYSENTER_EIP_MSR);
eval 'sub MSR_MCG_CAP () {0x179;}' unless defined(&MSR_MCG_CAP);
eval 'sub MSR_MCG_STATUS () {0x17a;}' unless defined(&MSR_MCG_STATUS);
eval 'sub MSR_MCG_CTL () {0x17b;}' unless defined(&MSR_MCG_CTL);
eval 'sub MSR_EVNTSEL0 () {0x186;}' unless defined(&MSR_EVNTSEL0);
eval 'sub MSR_EVNTSEL1 () {0x187;}' unless defined(&MSR_EVNTSEL1);
eval 'sub MSR_THERM_CONTROL () {0x19a;}' unless defined(&MSR_THERM_CONTROL);
eval 'sub MSR_THERM_INTERRUPT () {0x19b;}' unless defined(&MSR_THERM_INTERRUPT);
eval 'sub MSR_THERM_STATUS () {0x19c;}' unless defined(&MSR_THERM_STATUS);
eval 'sub MSR_IA32_MISC_ENABLE () {0x1a0;}' unless defined(&MSR_IA32_MISC_ENABLE);
eval 'sub MSR_IA32_TEMPERATURE_TARGET () {0x1a2;}' unless defined(&MSR_IA32_TEMPERATURE_TARGET);
eval 'sub MSR_DEBUGCTLMSR () {0x1d9;}' unless defined(&MSR_DEBUGCTLMSR);
eval 'sub MSR_LASTBRANCHFROMIP () {0x1db;}' unless defined(&MSR_LASTBRANCHFROMIP);
eval 'sub MSR_LASTBRANCHTOIP () {0x1dc;}' unless defined(&MSR_LASTBRANCHTOIP);
eval 'sub MSR_LASTINTFROMIP () {0x1dd;}' unless defined(&MSR_LASTINTFROMIP);
eval 'sub MSR_LASTINTTOIP () {0x1de;}' unless defined(&MSR_LASTINTTOIP);
eval 'sub MSR_ROB_CR_BKUPTMPDR6 () {0x1e0;}' unless defined(&MSR_ROB_CR_BKUPTMPDR6);
eval 'sub MSR_MTRRVarBase () {0x200;}' unless defined(&MSR_MTRRVarBase);
eval 'sub MSR_MTRR64kBase () {0x250;}' unless defined(&MSR_MTRR64kBase);
eval 'sub MSR_MTRR16kBase () {0x258;}' unless defined(&MSR_MTRR16kBase);
eval 'sub MSR_MTRR4kBase () {0x268;}' unless defined(&MSR_MTRR4kBase);
eval 'sub MSR_PAT () {0x277;}' unless defined(&MSR_PAT);
eval 'sub MSR_MC0_CTL2 () {0x280;}' unless defined(&MSR_MC0_CTL2);
eval 'sub MSR_MTRRdefType () {0x2ff;}' unless defined(&MSR_MTRRdefType);
eval 'sub MSR_MC0_CTL () {0x400;}' unless defined(&MSR_MC0_CTL);
eval 'sub MSR_MC0_STATUS () {0x401;}' unless defined(&MSR_MC0_STATUS);
eval 'sub MSR_MC0_ADDR () {0x402;}' unless defined(&MSR_MC0_ADDR);
eval 'sub MSR_MC0_MISC () {0x403;}' unless defined(&MSR_MC0_MISC);
eval 'sub MSR_MC1_CTL () {0x404;}' unless defined(&MSR_MC1_CTL);
eval 'sub MSR_MC1_STATUS () {0x405;}' unless defined(&MSR_MC1_STATUS);
eval 'sub MSR_MC1_ADDR () {0x406;}' unless defined(&MSR_MC1_ADDR);
eval 'sub MSR_MC1_MISC () {0x407;}' unless defined(&MSR_MC1_MISC);
eval 'sub MSR_MC2_CTL () {0x408;}' unless defined(&MSR_MC2_CTL);
eval 'sub MSR_MC2_STATUS () {0x409;}' unless defined(&MSR_MC2_STATUS);
eval 'sub MSR_MC2_ADDR () {0x40a;}' unless defined(&MSR_MC2_ADDR);
eval 'sub MSR_MC2_MISC () {0x40b;}' unless defined(&MSR_MC2_MISC);
eval 'sub MSR_MC3_CTL () {0x40c;}' unless defined(&MSR_MC3_CTL);
eval 'sub MSR_MC3_STATUS () {0x40d;}' unless defined(&MSR_MC3_STATUS);
eval 'sub MSR_MC3_ADDR () {0x40e;}' unless defined(&MSR_MC3_ADDR);
eval 'sub MSR_MC3_MISC () {0x40f;}' unless defined(&MSR_MC3_MISC);
eval 'sub MSR_MC4_CTL () {0x410;}' unless defined(&MSR_MC4_CTL);
eval 'sub MSR_MC4_STATUS () {0x411;}' unless defined(&MSR_MC4_STATUS);
eval 'sub MSR_MC4_ADDR () {0x412;}' unless defined(&MSR_MC4_ADDR);
eval 'sub MSR_MC4_MISC () {0x413;}' unless defined(&MSR_MC4_MISC);
eval 'sub APICBASE_RESERVED () {0x6ff;}' unless defined(&APICBASE_RESERVED);
eval 'sub APICBASE_BSP () {0x100;}' unless defined(&APICBASE_BSP);
eval 'sub APICBASE_ENABLED () {0x800;}' unless defined(&APICBASE_ENABLED);
eval 'sub APICBASE_ADDRESS () {0xfffff000;}' unless defined(&APICBASE_ADDRESS);
eval 'sub PAT_UNCACHEABLE () {0x;}' unless defined(&PAT_UNCACHEABLE);
eval 'sub PAT_WRITE_COMBINING () {0x1;}' unless defined(&PAT_WRITE_COMBINING);
eval 'sub PAT_WRITE_THROUGH () {0x4;}' unless defined(&PAT_WRITE_THROUGH);
eval 'sub PAT_WRITE_PROTECTED () {0x5;}' unless defined(&PAT_WRITE_PROTECTED);
eval 'sub PAT_WRITE_BACK () {0x6;}' unless defined(&PAT_WRITE_BACK);
eval 'sub PAT_UNCACHED () {0x7;}' unless defined(&PAT_UNCACHED);
eval 'sub PAT_VALUE {
my($i, $m) = @_;
eval q((($m) << (8* ($i))));
}' unless defined(&PAT_VALUE);
eval 'sub PAT_MASK {
my($i) = @_;
eval q( &PAT_VALUE($i, 0xff));
}' unless defined(&PAT_MASK);
eval 'sub MTRR_UNCACHEABLE () {0x;}' unless defined(&MTRR_UNCACHEABLE);
eval 'sub MTRR_WRITE_COMBINING () {0x1;}' unless defined(&MTRR_WRITE_COMBINING);
eval 'sub MTRR_WRITE_THROUGH () {0x4;}' unless defined(&MTRR_WRITE_THROUGH);
eval 'sub MTRR_WRITE_PROTECTED () {0x5;}' unless defined(&MTRR_WRITE_PROTECTED);
eval 'sub MTRR_WRITE_BACK () {0x6;}' unless defined(&MTRR_WRITE_BACK);
eval 'sub MTRR_N64K () {8;}' unless defined(&MTRR_N64K);
eval 'sub MTRR_N16K () {16;}' unless defined(&MTRR_N16K);
eval 'sub MTRR_N4K () {64;}' unless defined(&MTRR_N4K);
eval 'sub MTRR_CAP_WC () {0x400;}' unless defined(&MTRR_CAP_WC);
eval 'sub MTRR_CAP_FIXED () {0x100;}' unless defined(&MTRR_CAP_FIXED);
eval 'sub MTRR_CAP_VCNT () {0xff;}' unless defined(&MTRR_CAP_VCNT);
eval 'sub MTRR_DEF_ENABLE () {0x800;}' unless defined(&MTRR_DEF_ENABLE);
eval 'sub MTRR_DEF_FIXED_ENABLE () {0x400;}' unless defined(&MTRR_DEF_FIXED_ENABLE);
eval 'sub MTRR_DEF_TYPE () {0xff;}' unless defined(&MTRR_DEF_TYPE);
eval 'sub MTRR_PHYSBASE_PHYSBASE () {0xffffffffff000;}' unless defined(&MTRR_PHYSBASE_PHYSBASE);
eval 'sub MTRR_PHYSBASE_TYPE () {0xff;}' unless defined(&MTRR_PHYSBASE_TYPE);
eval 'sub MTRR_PHYSMASK_PHYSMASK () {0xffffffffff000;}' unless defined(&MTRR_PHYSMASK_PHYSMASK);
eval 'sub MTRR_PHYSMASK_VALID () {0x800;}' unless defined(&MTRR_PHYSMASK_VALID);
eval 'sub PCR0 () {0x20;}' unless defined(&PCR0);
eval 'sub PCR0_RSTK () {0x1;}' unless defined(&PCR0_RSTK);
eval 'sub PCR0_BTB () {0x2;}' unless defined(&PCR0_BTB);
eval 'sub PCR0_LOOP () {0x4;}' unless defined(&PCR0_LOOP);
eval 'sub PCR0_AIS () {0x8;}' unless defined(&PCR0_AIS);
eval 'sub PCR0_MLR () {0x10;}' unless defined(&PCR0_MLR);
eval 'sub PCR0_BTBRT () {0x40;}' unless defined(&PCR0_BTBRT);
eval 'sub PCR0_LSSER () {0x80;}' unless defined(&PCR0_LSSER);
eval 'sub DIR0 () {0xfe;}' unless defined(&DIR0);
eval 'sub DIR1 () {0xff;}' unless defined(&DIR1);
eval 'sub MCG_CAP_COUNT () {0xff;}' unless defined(&MCG_CAP_COUNT);
eval 'sub MCG_CAP_CTL_P () {0x100;}' unless defined(&MCG_CAP_CTL_P);
eval 'sub MCG_CAP_EXT_P () {0x200;}' unless defined(&MCG_CAP_EXT_P);
eval 'sub MCG_CAP_CMCI_P () {0x400;}' unless defined(&MCG_CAP_CMCI_P);
eval 'sub MCG_CAP_TES_P () {0x800;}' unless defined(&MCG_CAP_TES_P);
eval 'sub MCG_CAP_EXT_CNT () {0xff0000;}' unless defined(&MCG_CAP_EXT_CNT);
eval 'sub MCG_CAP_SER_P () {0x1000000;}' unless defined(&MCG_CAP_SER_P);
eval 'sub MCG_STATUS_RIPV () {0x1;}' unless defined(&MCG_STATUS_RIPV);
eval 'sub MCG_STATUS_EIPV () {0x2;}' unless defined(&MCG_STATUS_EIPV);
eval 'sub MCG_STATUS_MCIP () {0x4;}' unless defined(&MCG_STATUS_MCIP);
eval 'sub MCG_CTL_ENABLE () {0xffffffffffffffff;}' unless defined(&MCG_CTL_ENABLE);
eval 'sub MCG_CTL_DISABLE () {0x;}' unless defined(&MCG_CTL_DISABLE);
eval 'sub MSR_MC_CTL {
my($x) = @_;
eval q(( &MSR_MC0_CTL + ($x) * 4));
}' unless defined(&MSR_MC_CTL);
eval 'sub MSR_MC_STATUS {
my($x) = @_;
eval q(( &MSR_MC0_STATUS + ($x) * 4));
}' unless defined(&MSR_MC_STATUS);
eval 'sub MSR_MC_ADDR {
my($x) = @_;
eval q(( &MSR_MC0_ADDR + ($x) * 4));
}' unless defined(&MSR_MC_ADDR);
eval 'sub MSR_MC_MISC {
my($x) = @_;
eval q(( &MSR_MC0_MISC + ($x) * 4));
}' unless defined(&MSR_MC_MISC);
eval 'sub MSR_MC_CTL2 {
my($x) = @_;
eval q(( &MSR_MC0_CTL2 + ($x)));
}' unless defined(&MSR_MC_CTL2);
eval 'sub MC_STATUS_MCA_ERROR () {0xffff;}' unless defined(&MC_STATUS_MCA_ERROR);
eval 'sub MC_STATUS_MODEL_ERROR () {0xffff0000;}' unless defined(&MC_STATUS_MODEL_ERROR);
eval 'sub MC_STATUS_OTHER_INFO () {0x1ffffff00000000;}' unless defined(&MC_STATUS_OTHER_INFO);
eval 'sub MC_STATUS_COR_COUNT () {0x1fffc000000000;}' unless defined(&MC_STATUS_COR_COUNT);
eval 'sub MC_STATUS_TES_STATUS () {0x60000000000000;}' unless defined(&MC_STATUS_TES_STATUS);
eval 'sub MC_STATUS_AR () {0x80000000000000;}' unless defined(&MC_STATUS_AR);
eval 'sub MC_STATUS_S () {0x100000000000000;}' unless defined(&MC_STATUS_S);
eval 'sub MC_STATUS_PCC () {0x200000000000000;}' unless defined(&MC_STATUS_PCC);
eval 'sub MC_STATUS_ADDRV () {0x400000000000000;}' unless defined(&MC_STATUS_ADDRV);
eval 'sub MC_STATUS_MISCV () {0x800000000000000;}' unless defined(&MC_STATUS_MISCV);
eval 'sub MC_STATUS_EN () {0x1000000000000000;}' unless defined(&MC_STATUS_EN);
eval 'sub MC_STATUS_UC () {0x2000000000000000;}' unless defined(&MC_STATUS_UC);
eval 'sub MC_STATUS_OVER () {0x4000000000000000;}' unless defined(&MC_STATUS_OVER);
eval 'sub MC_STATUS_VAL () {0x8000000000000000;}' unless defined(&MC_STATUS_VAL);
eval 'sub MC_MISC_RA_LSB () {0x3f;}' unless defined(&MC_MISC_RA_LSB);
eval 'sub MC_MISC_ADDRESS_MODE () {0x1c0;}' unless defined(&MC_MISC_ADDRESS_MODE);
eval 'sub MC_CTL2_THRESHOLD () {0x7fff;}' unless defined(&MC_CTL2_THRESHOLD);
eval 'sub MC_CTL2_CMCI_EN () {0x40000000;}' unless defined(&MC_CTL2_CMCI_EN);
eval 'sub NCR1 () {0xc4;}' unless defined(&NCR1);
eval 'sub NCR2 () {0xc7;}' unless defined(&NCR2);
eval 'sub NCR3 () {0xca;}' unless defined(&NCR3);
eval 'sub NCR4 () {0xcd;}' unless defined(&NCR4);
eval 'sub NCR_SIZE_0K () {0;}' unless defined(&NCR_SIZE_0K);
eval 'sub NCR_SIZE_4K () {1;}' unless defined(&NCR_SIZE_4K);
eval 'sub NCR_SIZE_8K () {2;}' unless defined(&NCR_SIZE_8K);
eval 'sub NCR_SIZE_16K () {3;}' unless defined(&NCR_SIZE_16K);
eval 'sub NCR_SIZE_32K () {4;}' unless defined(&NCR_SIZE_32K);
eval 'sub NCR_SIZE_64K () {5;}' unless defined(&NCR_SIZE_64K);
eval 'sub NCR_SIZE_128K () {6;}' unless defined(&NCR_SIZE_128K);
eval 'sub NCR_SIZE_256K () {7;}' unless defined(&NCR_SIZE_256K);
eval 'sub NCR_SIZE_512K () {8;}' unless defined(&NCR_SIZE_512K);
eval 'sub NCR_SIZE_1M () {9;}' unless defined(&NCR_SIZE_1M);
eval 'sub NCR_SIZE_2M () {10;}' unless defined(&NCR_SIZE_2M);
eval 'sub NCR_SIZE_4M () {11;}' unless defined(&NCR_SIZE_4M);
eval 'sub NCR_SIZE_8M () {12;}' unless defined(&NCR_SIZE_8M);
eval 'sub NCR_SIZE_16M () {13;}' unless defined(&NCR_SIZE_16M);
eval 'sub NCR_SIZE_32M () {14;}' unless defined(&NCR_SIZE_32M);
eval 'sub NCR_SIZE_4G () {15;}' unless defined(&NCR_SIZE_4G);
eval 'sub ARR0 () {0xc4;}' unless defined(&ARR0);
eval 'sub ARR1 () {0xc7;}' unless defined(&ARR1);
eval 'sub ARR2 () {0xca;}' unless defined(&ARR2);
eval 'sub ARR3 () {0xcd;}' unless defined(&ARR3);
eval 'sub ARR4 () {0xd0;}' unless defined(&ARR4);
eval 'sub ARR5 () {0xd3;}' unless defined(&ARR5);
eval 'sub ARR6 () {0xd6;}' unless defined(&ARR6);
eval 'sub ARR7 () {0xd9;}' unless defined(&ARR7);
eval 'sub ARR_SIZE_0K () {0;}' unless defined(&ARR_SIZE_0K);
eval 'sub ARR_SIZE_4K () {1;}' unless defined(&ARR_SIZE_4K);
eval 'sub ARR_SIZE_8K () {2;}' unless defined(&ARR_SIZE_8K);
eval 'sub ARR_SIZE_16K () {3;}' unless defined(&ARR_SIZE_16K);
eval 'sub ARR_SIZE_32K () {4;}' unless defined(&ARR_SIZE_32K);
eval 'sub ARR_SIZE_64K () {5;}' unless defined(&ARR_SIZE_64K);
eval 'sub ARR_SIZE_128K () {6;}' unless defined(&ARR_SIZE_128K);
eval 'sub ARR_SIZE_256K () {7;}' unless defined(&ARR_SIZE_256K);
eval 'sub ARR_SIZE_512K () {8;}' unless defined(&ARR_SIZE_512K);
eval 'sub ARR_SIZE_1M () {9;}' unless defined(&ARR_SIZE_1M);
eval 'sub ARR_SIZE_2M () {10;}' unless defined(&ARR_SIZE_2M);
eval 'sub ARR_SIZE_4M () {11;}' unless defined(&ARR_SIZE_4M);
eval 'sub ARR_SIZE_8M () {12;}' unless defined(&ARR_SIZE_8M);
eval 'sub ARR_SIZE_16M () {13;}' unless defined(&ARR_SIZE_16M);
eval 'sub ARR_SIZE_32M () {14;}' unless defined(&ARR_SIZE_32M);
eval 'sub ARR_SIZE_4G () {15;}' unless defined(&ARR_SIZE_4G);
eval 'sub RCR0 () {0xdc;}' unless defined(&RCR0);
eval 'sub RCR1 () {0xdd;}' unless defined(&RCR1);
eval 'sub RCR2 () {0xde;}' unless defined(&RCR2);
eval 'sub RCR3 () {0xdf;}' unless defined(&RCR3);
eval 'sub RCR4 () {0xe0;}' unless defined(&RCR4);
eval 'sub RCR5 () {0xe1;}' unless defined(&RCR5);
eval 'sub RCR6 () {0xe2;}' unless defined(&RCR6);
eval 'sub RCR7 () {0xe3;}' unless defined(&RCR7);
eval 'sub RCR_RCD () {0x1;}' unless defined(&RCR_RCD);
eval 'sub RCR_RCE () {0x1;}' unless defined(&RCR_RCE);
eval 'sub RCR_WWO () {0x2;}' unless defined(&RCR_WWO);
eval 'sub RCR_WL () {0x4;}' unless defined(&RCR_WL);
eval 'sub RCR_WG () {0x8;}' unless defined(&RCR_WG);
eval 'sub RCR_WT () {0x10;}' unless defined(&RCR_WT);
eval 'sub RCR_NLB () {0x20;}' unless defined(&RCR_NLB);
eval 'sub AMD_WT_ALLOC_TME () {0x40000;}' unless defined(&AMD_WT_ALLOC_TME);
eval 'sub AMD_WT_ALLOC_PRE () {0x20000;}' unless defined(&AMD_WT_ALLOC_PRE);
eval 'sub AMD_WT_ALLOC_FRE () {0x10000;}' unless defined(&AMD_WT_ALLOC_FRE);
eval 'sub MSR_EFER () {0xc0000080;}' unless defined(&MSR_EFER);
eval 'sub MSR_STAR () {0xc0000081;}' unless defined(&MSR_STAR);
eval 'sub MSR_LSTAR () {0xc0000082;}' unless defined(&MSR_LSTAR);
eval 'sub MSR_CSTAR () {0xc0000083;}' unless defined(&MSR_CSTAR);
eval 'sub MSR_SF_MASK () {0xc0000084;}' unless defined(&MSR_SF_MASK);
eval 'sub MSR_FSBASE () {0xc0000100;}' unless defined(&MSR_FSBASE);
eval 'sub MSR_GSBASE () {0xc0000101;}' unless defined(&MSR_GSBASE);
eval 'sub MSR_KGSBASE () {0xc0000102;}' unless defined(&MSR_KGSBASE);
eval 'sub MSR_PERFEVSEL0 () {0xc0010000;}' unless defined(&MSR_PERFEVSEL0);
eval 'sub MSR_PERFEVSEL1 () {0xc0010001;}' unless defined(&MSR_PERFEVSEL1);
eval 'sub MSR_PERFEVSEL2 () {0xc0010002;}' unless defined(&MSR_PERFEVSEL2);
eval 'sub MSR_PERFEVSEL3 () {0xc0010003;}' unless defined(&MSR_PERFEVSEL3);
undef(&MSR_PERFCTR0) if defined(&MSR_PERFCTR0);
undef(&MSR_PERFCTR1) if defined(&MSR_PERFCTR1);
eval 'sub MSR_PERFCTR0 () {0xc0010004;}' unless defined(&MSR_PERFCTR0);
eval 'sub MSR_PERFCTR1 () {0xc0010005;}' unless defined(&MSR_PERFCTR1);
eval 'sub MSR_PERFCTR2 () {0xc0010006;}' unless defined(&MSR_PERFCTR2);
eval 'sub MSR_PERFCTR3 () {0xc0010007;}' unless defined(&MSR_PERFCTR3);
eval 'sub MSR_SYSCFG () {0xc0010010;}' unless defined(&MSR_SYSCFG);
eval 'sub MSR_HWCR () {0xc0010015;}' unless defined(&MSR_HWCR);
eval 'sub MSR_IORRBASE0 () {0xc0010016;}' unless defined(&MSR_IORRBASE0);
eval 'sub MSR_IORRMASK0 () {0xc0010017;}' unless defined(&MSR_IORRMASK0);
eval 'sub MSR_IORRBASE1 () {0xc0010018;}' unless defined(&MSR_IORRBASE1);
eval 'sub MSR_IORRMASK1 () {0xc0010019;}' unless defined(&MSR_IORRMASK1);
eval 'sub MSR_TOP_MEM () {0xc001001a;}' unless defined(&MSR_TOP_MEM);
eval 'sub MSR_TOP_MEM2 () {0xc001001d;}' unless defined(&MSR_TOP_MEM2);
eval 'sub MSR_K8_UCODE_UPDATE () {0xc0010020;}' unless defined(&MSR_K8_UCODE_UPDATE);
eval 'sub MSR_MC0_CTL_MASK () {0xc0010044;}' unless defined(&MSR_MC0_CTL_MASK);
eval 'sub VIA_HAS_RNG () {1;}' unless defined(&VIA_HAS_RNG);
eval 'sub VIA_HAS_AES () {1;}' unless defined(&VIA_HAS_AES);
eval 'sub VIA_HAS_SHA () {2;}' unless defined(&VIA_HAS_SHA);
eval 'sub VIA_HAS_MM () {4;}' unless defined(&VIA_HAS_MM);
eval 'sub VIA_HAS_AESCTR () {8;}' unless defined(&VIA_HAS_AESCTR);
eval 'sub VIA_CPUID_HAS_RNG () {0x4;}' unless defined(&VIA_CPUID_HAS_RNG);
eval 'sub VIA_CPUID_DO_RNG () {0x8;}' unless defined(&VIA_CPUID_DO_RNG);
eval 'sub VIA_CPUID_HAS_ACE () {0x40;}' unless defined(&VIA_CPUID_HAS_ACE);
eval 'sub VIA_CPUID_DO_ACE () {0x80;}' unless defined(&VIA_CPUID_DO_ACE);
eval 'sub VIA_CPUID_HAS_ACE2 () {0x100;}' unless defined(&VIA_CPUID_HAS_ACE2);
eval 'sub VIA_CPUID_DO_ACE2 () {0x200;}' unless defined(&VIA_CPUID_DO_ACE2);
eval 'sub VIA_CPUID_HAS_PHE () {0x400;}' unless defined(&VIA_CPUID_HAS_PHE);
eval 'sub VIA_CPUID_DO_PHE () {0x800;}' unless defined(&VIA_CPUID_DO_PHE);
eval 'sub VIA_CPUID_HAS_PMM () {0x1000;}' unless defined(&VIA_CPUID_HAS_PMM);
eval 'sub VIA_CPUID_DO_PMM () {0x2000;}' unless defined(&VIA_CPUID_DO_PMM);
eval 'sub VIA_CRYPT_CWLO_ROUND_M () {0xf;}' unless defined(&VIA_CRYPT_CWLO_ROUND_M);
eval 'sub VIA_CRYPT_CWLO_ALG_M () {0x70;}' unless defined(&VIA_CRYPT_CWLO_ALG_M);
eval 'sub VIA_CRYPT_CWLO_ALG_AES () {0x;}' unless defined(&VIA_CRYPT_CWLO_ALG_AES);
eval 'sub VIA_CRYPT_CWLO_KEYGEN_M () {0x80;}' unless defined(&VIA_CRYPT_CWLO_KEYGEN_M);
eval 'sub VIA_CRYPT_CWLO_KEYGEN_HW () {0x;}' unless defined(&VIA_CRYPT_CWLO_KEYGEN_HW);
eval 'sub VIA_CRYPT_CWLO_KEYGEN_SW () {0x80;}' unless defined(&VIA_CRYPT_CWLO_KEYGEN_SW);
eval 'sub VIA_CRYPT_CWLO_NORMAL () {0x;}' unless defined(&VIA_CRYPT_CWLO_NORMAL);
eval 'sub VIA_CRYPT_CWLO_INTERMEDIATE () {0x100;}' unless defined(&VIA_CRYPT_CWLO_INTERMEDIATE);
eval 'sub VIA_CRYPT_CWLO_ENCRYPT () {0x;}' unless defined(&VIA_CRYPT_CWLO_ENCRYPT);
eval 'sub VIA_CRYPT_CWLO_DECRYPT () {0x200;}' unless defined(&VIA_CRYPT_CWLO_DECRYPT);
eval 'sub VIA_CRYPT_CWLO_KEY128 () {0xa;}' unless defined(&VIA_CRYPT_CWLO_KEY128);
eval 'sub VIA_CRYPT_CWLO_KEY192 () {0x40c;}' unless defined(&VIA_CRYPT_CWLO_KEY192);
eval 'sub VIA_CRYPT_CWLO_KEY256 () {0x80e;}' unless defined(&VIA_CRYPT_CWLO_KEY256);
}
1;